DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on 6/30/2023.
Drawings
The Drawings have been considered and placed in the record on file and are in compliance with USPTO requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-12, 14-16, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-12, and 16-18 of U.S. Patent No. 12,334,018. Although the claims at issue are not identical, they are not patentably distinct from each other.
Application 19/206228
Patent No. 12,334,018
1. A display apparatus comprising:
a shared circuit connected to a reference voltage line and configured to output a reference voltage, wherein the shared circuit includes a first transistor configured to operate based on a first signal, a second transistor connected to the first transistor and configured to operate based on a second signal, and a third transistor configured to operate based on a third signal and connected to the second transistor; and
a first pixel circuit including:
a driving transistor;
[(from above) a third transistor configured to operate based on a third signal and connected to the second transistor;]
a fourth-first transistor configured to operate based on a first control signal;
a fourth-second transistor configured to operate based on a second control signal;
a first light-emitting element connected to the fourth-first transistor; and
a second light-emitting element connected to the fourth-second transistor.
1. A display apparatus comprising:
a mode controller configured to generate a first control signal and a second control signal;
a gate drive circuit configured to generate a light-emitting signal, a first scan signal, and a second scan signal;
a shared circuit connected to a reference voltage line and configured to provide a reference voltage, wherein the shared circuit includes a first transistor configured to operate based on the first scan signal, and a second transistor connected to the first transistor in series and configured to operate based on the second scan signal; and
[(from below) a third transistor configured to operate based on the light-emitting signal and connected to the second transistor; ]
a first pixel circuit connected to the mode controller and the gate drive circuit, wherein the first pixel circuit comprises:
a driving transistor;
a third transistor configured to operate based on the light-emitting signal and connected to the second transistor;
a fourth-first transistor configured to operate based on the first control signal;
a fourth-second transistor configured to operate based on the second control signal;
a first light-emitting element connected to the fourth-first transistor;
a second light-emitting element connected to the fourth-second transistor; and
a capacitor connected to the first transistor, the second transistor, the third transistor, and the driving transistor.
Application 19/206228
Claim 2
Claim 3
Claim 4
Claim 5
Claim 6
Claim 7
Claim 8
Claim 9
Claim 10
Patent No. 12,334,018
Claim 16
Claim 3
Claim 4
Claim 5
Claim 6
Claim 7
Claim 8
Claim 9
Claim 10
Application 19/206228
Claim 11
Claim 12
Claim 14
Claim 15
Claim 16
Claim 18
Patent No. 12,334,018
Claim 11
Claim 12
Claim 1
Claim 16
Claim 17+18
Claim 18
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 7-11, 13, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0038177 A1 hereinafter Kim).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to claim 1, Kim discloses a display apparatus comprising:
a shared circuit connected to a reference voltage line (see figure 5, reference voltage Vref) and configured to output a reference voltage, wherein the shared circuit includes a first transistor configured to operate based on a first signal (see figure 5, transistor T9 controlled by Scan(n)), a second transistor connected to the first transistor and configured to operate based on a second signal (see figure 5, transistor T10 controlled by Scan(n-1)), and a third transistor configured to operate based on a third signal and connected to the second transistor (see figure 5, transistor T8 controlled by EM0(n)); and
a first pixel circuit including:
a driving transistor (see figure 5, transistor DT);
a fourth-first transistor configured to operate based on a first control signal (see figure 5, transistor T1, controlled by EM1(n));
a fourth-second transistor configured to operate based on a second control signal (see figure 5, transistor T2, controlled by EM2(n));
a first light-emitting element connected to the fourth-first transistor (see figure 5, ED1); and
a second light-emitting element connected to the fourth-second transistor (see figure 5, ED2).
In regard to claim 4, as recited in claim 1, Kim further discloses wherein a first electrode of the first transistor is connected to the reference voltage line, and a second electrode of the first transistor is connected to the second transistor (see figure 5, transistor T9 is connected to Vref and to transistor T10).
In regards to claim 7, as recited in claim 1, Kim further discloses further comprising a fifth transistor connected to the driving transistor and a data voltage line (see figure 5, transistor T7 is connected to the driving transistor DT and a data voltage line Vdata); and
a sixth transistor connected to a gate electrode of the driving transistor (see figure 5, transistor T3 is connected to the gate electrode of the driving transistor DT).
In regards to claim 8, as recited in claim 1, Kim further discloses further comprising a seventh-first transistor connected to an initialization voltage line, the fourth-first transistor, and the first light-emitting element (see figure 5, transistor T51, connected to Vini, transistor T1, and ED1); and
a seventh-second transistor connected to the initialization voltage line, the fourth-second transistor, and the second light-emitting element (see figure 5, transistor T52, connected to Vini, transistor T2, and ED2).
In regards to claim 9, as recited in claim 8, Kim further discloses further comprising an eighth transistor connected to a gate electrode of the driving transistor, the seventh-first transistor, the seventh-second transistor, and the initialization voltage line (see figure 5, transistor T4, connected to gate of the driving transistor DT, T51, T52, and Vini).
In regards to claim 10, as recited in claim 1, Kim further discloses further comprising a ninth transistor connected to a high-potential voltage line, the second transistor, the third transistor, and the driving transistor (see figure 5, transistor T6, connected to ELVDD, T10, T8, and DT).
In regards to claim 11, as recited in claim 1, Kim further discloses wherein a first electrode of the fourth-first transistor and a first electrode of the fourth-second transistor are electrically connected to the driving transistor (see figure 5), a second electrode of the fourth-first transistor is connected to the first light-emitting element, and a second electrode of the fourth-second transistor is connected to the second light-emitting element (see figure 5, T1 connected to ED1 and T2 connected to ED2).
In regards to claim 13, as recited in claim 1, Kim further discloses further comprising: a mode controller configured to output the first control signal and the second control signal (see figure 11 and paragraph 0158, first and second mode controller 1111 and 1112). and a gate drive circuit configured to output a light-emitting signal, the first signal, and the second signal (see figure 2 and paragraph 0047, gate driver GD).
In regards to claim 14, as recited in claim 1, Kim further discloses wherein the first pixel circuit further includes a capacitor connected to the first transistor, the second transistor, the third transistor, and the driving transistor (see figure 5, capacitor C1 connected to T9, T10, T8, and DT).
Allowable Subject Matter
Claims 15-18 are allowed.
Claims 2, 3, 5, 6, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30.
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/CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628