Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 13, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
Regarding Fig. 2, reference Y and 19y are both pointing at the components of Fig. 2. Applicant needs to clarify which reference is pointing to which components clearly. It's unclear if reference 23 and 21 are within 19y.
Regarding Fig. 6, reference X and 19x are both pointing at the components of Fig. 2. Applicant needs to clarify which reference is pointing to which components clearly. It's unclear if reference 23 and 21 are within 19x.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 1 (lines 2-3 & 16-19) recites "a ramp voltage generation circuit configured to generate a ramp voltage on a basis of a first reference voltage", and "the ramp voltage generation circuit is configured to generate the ramp voltage on a basis of the lowest voltage among a second reference voltage based on the first reference voltage, the first signal, and the second signal". Per Fig. 6 below, the first limitation of the claim the ramp voltage generation circuit (22x) is configured to generate a ramp voltage (Vrmp), but it's unclear how this ramp voltage is configured on the basis of the first reference voltage (Vr1). The last limitation of the claim clearly shows that the ramp voltage (Vrmp) is generated on a basis of the lowest voltage (output of 26x) of the second reference voltage (Vr2) or the first signal (S1) or the second signal (S2). The first reference voltage enters a voltage divider (24) which generates an output of the second reference voltage (Vr2), and the first reference voltage (Vr1) enters the comparator (23) with the ramp voltage (Vrmp) to generate a clock signal (CLK). The examiner will be interpreting the first limitation of claim 1 as "a ramp voltage generation circuit configured to generate a ramp voltage.".
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Claims 2-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Liu (CN 113131901 A), hereinafter Liu.
Regarding Claim 1, Liu, as best understood, discloses an oscillation circuit [200/300] comprising: a ramp voltage generation circuit [310] configured to generate a ramp voltage [V1] on a basis of a first reference voltage [Vbg]; and a comparator [221] configured to generate a pulse-driven clock signal [CLK] according to the first reference voltage and the ramp voltage, wherein the ramp voltage generation circuit includes a first signal generation circuit [see figure 300 below] configured to generate a first signal [VL1] that rises or falls according to a duty ratio of a first pulse width modulation signal [Fig. 5; S1/S2] generated on a basis of a pulse period of the clock signal [Fig. 5], and a second signal generation circuit [see figure 300 below] configured to generate a second signal [VL2] that rises or falls in a direction opposite to the first signal [Fig. 5; S1/S2] according to the duty ratio of the first pulse width modulation signal, and the ramp voltage generation circuit is configured to generate the ramp voltage on a basis of the lowest voltage [paragraph 0055 (marked in English translation copy] among a second reference voltage [Vref] based on the first reference voltage, the first signal, and the second signal.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Noda (KR 20090125287 A), in view of Liu; hereinafter Noda, in view of Liu.
Regarding Claim 5, Noda, as best understood, discloses a power supply device [Fig. 1, 1] comprising: the oscillation circuit [6]; a pulse width modulation signal generation circuit [7/8] configured to generate a first pulse width modulation signal [(Sq)] on a basis of a pulse period; an output stage [M1/M2] configured to generate a switch voltage that is pulse-driven [voltage at node Lx] between a first logical value [(S1) at gate of M1] and a second logical value [(S1) at gate of M2] on a basis of a duty ratio of the first pulse width modulation signal; and a rectifying/smoothing circuit [L1/C1] configured to rectify and smooth the switch voltage to generate an output voltage [(Vout)]. Noda does not explicitly disclose the oscillation circuit according to claim 1.
However, Liu discloses the oscillation according to claim 1 [see Claim 1 rejection]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Noda in the invention of Liu, with the expected benefit of providing a stable clock signal. This method of improving Liu using Noda was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Noda. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liu and Noda to obtain the invention: incorporating the oscillator within the power supply device.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Akaho (JP 2023174083 A), in view of Liu; hereinafter Akaho, in view of Liu.
Regarding Claim 5, Akaho, as best understood, discloses a power supply device [Fig. 26, 1] comprising: the oscillation circuit [15]; a pulse width modulation signal generation circuit [CD] configured to generate a first pulse width modulation signal [S3] on a basis of a pulse period; an output stage [MM] configured to generate a switch voltage that is pulse-driven [Vsw] between a first logical value [G1] and a second logical value [G2] on a basis of a duty ratio of the first pulse width modulation signal; and a rectifying/smoothing circuit [3] configured to rectify and smooth the switch voltage to generate an output voltage [Vout]. Akaho does not explicitly disclose the oscillation circuit according to claim 1.
However, Liu discloses the oscillation according to claim 1 [see Claim 1 rejection]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Akaho in the invention of Liu, with the expected benefit of providing a stable clock signal. This method of improving Liu using Akaho was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Akaho. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liu and Akaho to obtain the invention: incorporating the oscillator within the power supply device.
Allowable Subject Matter
Claims 2-4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 2-4 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following are statements of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of the record does not disclose nor render obvious wherein the second signal generation circuit generates a second pulse width modulation signal obtained by inverting a logic level of the first pulse width modulation signal and generates the second signal according to the second pulse width modulation signal, as cited with the rest of the claimed limitation.
Regarding Claim 3, the prior art of the record does not disclose nor render obvious wherein the ramp voltage generation circuit further includes a ramp current generation circuit configured to generate a ramp current on the basis of the lowest voltage among the second reference voltage, the first signal, and the second signal, and a current-voltage conversion circuit configured to convert the ramp current into the ramp voltage, as cited with the rest of the claimed limitation.
Regarding Claim 4, the prior art of the record does not disclose nor render obvious wherein first signal becomes equal to or less than the second reference voltage in a state where an on-duty of the first pulse width modulation signal reaches a lower limit value, and the second signal becomes equal to or less than the second reference voltage in a state where the on-duty of the first pulse width modulation signal reaches an upper limit value, as cited with the rest of the claimed limitation..
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wadhwa et al. (US 20120319788 A1); Wachi et al. (JP 2022112806 A); Kawano et al. (US 20170310214 A1); Inoue (KR 20080021538 A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
Prosecution Insights