DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the recitation of “connectable” (line 12) is indefinite because it is unclear it is connected or not, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
In claim 10, the recitation of “the interrupted input” (line 3) lacks antecedent basis, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
In claim 14, the recitation of “the regenerative receiver” (line 3) lacks antecedent basis, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
In claim 15, the recitation of “the digital domain” (line 2) lacks antecedent basis, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
Claims 1-9, 11, 13 are indefinite because of the technical deficiencies of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, 9-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fu et al. (A supper-regenerative-oscillator wake-up receiver for underwater applications with improved PVT immunity), prior art cited by the applicant.
Regarding claim 1, Fu et al.’s figure 15 shows An electronic circuit configured to generate a ramped current signal (a current signal from all current sources at the summing nodes LC_SRO) for a receiver circuit (oscillator LC_SRO), the electronic circuit (1) comprising:- a first current cell (a first DFF, Q1 and a current source) comprising a first current source (a current source of a plurality current sources connected in parallel), a trigger input (input_driver) to activate the first current source (a current source of a plurality current sources connected in parallel) and a trigger output (output Q of first DFF),- a second current cell (a second DFF, Q2 and a current source) comprising a second current source (a second current source of a plurality current sources connected in parallel), a trigger input (a second DFF connected to the output of the first DFF) to activate the second current source (a second current source of a plurality current sources connected in parallel) and a trigger output (Q output of the second DFF), wherein the trigger output of the first current cell is connected to the trigger input of the second current cell , and- a current supply (a summing node of all the parallel current sources) connected to a supply input (input node of the oscillator LC_SRO) of the receiver circuit (the oscillator LC_SRO) and connectable with any of the first current source and the second current source (a plurality of current source) as called for in claim 1.
Regarding claim 2, wherein a supply current of the first current cell distinguishes from a supply current of the second current cell (each current sources is not the same as the other current source).
Regarding claim 3, wherein each one of the first current cell and the second current cell comprises a buffer (D-FFs) to transfer an input signal at the trigger input (CK) to the trigger output (Q of DFF) of the respective current cell after lapse of a predefined transition time (propagation delay time of the DFFs).
Regarding claim 4, wherein when activated by a signal at the trigger input (CK) of any of the first or second current cells the current source of the respective current cell is connected to the current supply.
Regarding claim 8, a receiver circuit (oscillator) comprising a supply input (input of the oscillator, and- and an electronic circuit (10) according to claim 1, wherein the current supply the electronic circuit is connected to the supply input .
Regarding claim 9, an oscillation detector (envelope detector; figure 2) connected to a feedback line (35), wherein the oscillation detector (32) is configured to detect the oscillation of the regenerative receiver and is further configured to generate and to transfer a feedback signal to the feedback line when the current at the supply input equals or exceeds the current needed for oscillation (dynamic comparator performs the comparation).
Regarding claim 10, the regenerative receiver according to claim 9 and comprising an electronic circuit, wherein the feedback line is connected to the interrupt inputs of the first current cell and the second current cell of the electronic circuit (via the logic AND gate).
Regarding claims 11-14, the electronic circuit of Fu et al.’s figure 15 anticipates all the methods steps recited in claims 11-14.
Regarding claim 15, insofar as being understood, comprising deriving or determining a ramp time interval in the digital domain by counting a number of activated current cells or activated current sources (the number of current source being activated determined how steep the ramp time is).
Claim(s) 1-4, 8, 11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sutardja (USP 6,462,688).
Regarding claim 1, Sutardja’s figure 13 shows An electronic circuit configured to generate a ramped current signal (Io) for a receiver circuit (circuit receiving Io), the electronic circuit comprising:- a first current cell (d1, 53b and a current source 53a) comprising a first current source (53a), a trigger input (Iin) to activate the first current source and a trigger output (output of d1),- a second current cell (d2, 54b, 54a) comprising a second current source (54a), a trigger input (input of 54b and d2) to activate the second current source and a trigger output (output of d2), wherein the trigger output of the first current cell is connected to the trigger input of the second current cell , and- a current supply (a summing node of all the parallel current sources) connected to a supply input (Io) of the receiver circuit and connectable with any of the first current source and the second current source as called for in claim 1.
Regarding claim 2, wherein a supply current of the first current cell distinguishes from a supply current of the second current cell (each current sources is not the same as the other current source).
Regarding claim 3, wherein each one of the first current cell and the second current cell comprises a buffer (ds) to transfer an input signal at the trigger input to the trigger output of the respective current cell after lapse of a predefined transition time (propagation delay time of ds).
Regarding claim 4, wherein when activated by a signal at the trigger input (In) of any of the first or second current cells the current source of the respective current cell is connected to the current supply.
Regarding claim 8, a receiver circuit (not shown) comprising a supply input (input of the oscillator, and- and an electronic circuit according to claim 1, wherein the current supply the electronic circuit is connected to the supply input (Io).
Regarding claims 11-14, the electronic circuit Sutardja’s figure 13 anticipates all the methods steps recited in claims 11-14.
Regarding claim 15, insofar as being understood, comprising deriving or determining a ramp time interval in the digital domain by counting a number of activated current cells or activated current sources (the number of current source being activated determined how steep the ramp time is).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fu et al. (A supper-regenerative-oscillator wake-up receiver for underwater applications with improved PVT immunity), prior art cited by the applicant.
Regarding claim 5, Fu et al.’s figure 15 discloses an electronic circuit comprising all the aspects of the present invention except Fu et al. reference shows only the first current cell includes a buffer (AND gate) transferring the input trigger (output from the comparator) to the input of the first current cell (CK) instead of having each of the current cells includes a buffer as called for in claim 5. However, one skilled in the art would have recognized that including a buffer (logic AND gate) in each current cell stage would allow each subsequent stages activated/deactivated when needed in order to save power consumption. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include a buffer (logic AND gate ) in each subsequent current cell stages for the purpose of saving power consumption.
Regarding claim 6, the logic unit further comprises and a current cell indicator output (output of the NOT gates), wherein a signal at the current cell indicator output is indicative of an activation of the current source (connecting the switches).
Regarding claim 7, wherein the logic unit is coupled to the trigger input (output from the comparator) and wherein the logic unit (AND) is operable to provide an indication signal at the current cell indicator output (output from the inverters) in response to an input signal at the trigger input.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja (USP 6,462,688) in view of Liu et al. (US 2016/0062430).
Regarding claim 15, Sutardja’s figure 13 shows an electronic comprising all the aspects of the present invention as noted above except each one of the first current cell and the second current cell comprises a logic unit , the logic unit comprising an interrupt input which is operable to decouple the current source from the trigger input in response to receive an interrupt signal at the interrupt input as called for in claim 5.
Liu et al.’s figure 8 shows a buffer (logic gate AND) coupled to receive an interrupt signal (enable signal 110) which is operable to decouple the current source (1, R) from the trigger input in response to receive an interrupt signal at the interrupt input. This arrangement allows a control of activate/deactivate a current cell, thus, to reduce power consumption. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Liu et al.’s buffer in Sutardja’s circuit arrangement for the purpose of activating/deactivating current cells in order to reduce power consumption.
Regarding claim 6, the logic unit further comprises and a current cell indicator output (output of the AND gates), wherein a signal at the current cell indicator output is indicative of an activation of the current source.
Regarding claim 7, wherein the logic unit is coupled to the trigger input and wherein the logic unit (AND) is operable to provide an indication signal at the current cell indicator output in response to an input signal at the trigger input.
Claim(s) 1, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Casagrande et al. (US 2023/0102272) in view of over Sutardja (USP 6,462,688)
Regarding claims 1 and 8-9, Casagrande et al.’s figure 1 shows a regenerative receiver (VCO) with supply current input (I_VCO), an electronic circuit (7) for supply a ramped current (I_VCO) to the regenerative receiver; an oscillation detector (6) connected to a feedback line (stop), wherein the oscillation detector (6) is configured to detect the oscillation of the regenerative receiver (VCO) and is further configured to generate and to transfer a feedback signal to the feedback line when the current at the supply input equals or exceeds the current needed for oscillation (paragraphs 0018-0019).
Sutardja’s figure 13 discloses an electronic circuit for providing a desired/accurate ramped current comprising a first current cell (d1, 53b and a current source 53a) comprising a first current source (53a), a trigger input (Iin) to activate the first current source and a trigger output (output of d1),- a second current cell (d2, 54b, 54a) comprising a second current source (54a), a trigger input (input of 54b and d2) to activate the second current source and a trigger output (output of d2), wherein the trigger output of the first current cell is connected to the trigger input of the second current cell , and- a current supply (a summing node of all the parallel current sources) connected to a supply input (Io) of the receiver circuit and connectable with any of the first current source and the second current source. Therefore, it would have been obvious to person skilled in the before the effective filing date of the invention to replace Casagrande et al.’s electronic circuit (7) with Sutardja’s electronic circuit for the purpose of providing a desired ramped output current as taught by Sutardja reference.
Regarding claim 10, wherein the feedback line (stop) is connected to the interrupt inputs (input of the electronic circuit 7) of the first current cell and the second current cell of the electronic circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been carefully considered.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2836
6/3/2026
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