DETAILED ACTION
Claims 1-30 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/13/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1, 2, 5-15, 20-24 and 27-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5-15, 20-24 and 27-30 of U.S. Patent No. 12,308,958, hereinafter ‘958. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application is merely an obvious rendition of ‘958. A comparison of independent claim 1, showing the differences is shown below where the crossed through words are from the current application and the underlined words are from ‘958.
1. A transmitting device, comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the transmitting device to: perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein the base graph compa punctured variable node of the plurality of variable nodes corresponds to each of one or more punctcheck nodes of the plurality of check nodes via a pluriable nodality of edges; encode a plurality of information nodes and a plurality of parity nodes according to the lifted graph; and transmit a signal comprising a plurality of information bits and a plurality of parity bits based at least in part on encoding the plurality of information nodes and the plurality of parity nodes.
Allowable Subject Matter
Claims 1-30 would be allowable if rewritten, amended or with the proper filing of an electronic Terminal Disclaimer to overcome the nonstatutory double patenting rejection set forth in this Office action.
The following is an Examiner’s Statement of Reasons for Allowance:
The present invention relates to improved methods, systems, devices, and apparatuses that support fast converging low-density parity-check (LDPC) techniques.
The claimed invention as set forth in claim 1 recites features such as:
A transmitting device, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the transmitting device to:
perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein the base graph comprises one or more punctured variable nodes;
encode a plurality of information nodes and a plurality of parity nodes according to the lifted graph; and
transmit a signal comprising a plurality of information bits and a plurality of parity bits based at least in part on encoding the plurality of information nodes and the plurality of parity nodes.
The prior arts of record, namely Soriaga et al. (US-20190052400), teach FIG. 3 illustrates an example of a bipartite graph 300 showing liftings of three copies of the bipartite graph 200-a of FIG. 2A in accordance with various aspects of the present disclosure. Three copies (comprising first copy with variable node 210 and check node 220, second copy with variable node 210′ and check node 220′, and third copy with variable node 210″ and check node 220″) may be interconnected by permuting like edges among the copies. If the permutations are restricted to cyclic permutations, then the resulting bipartite graph 300 corresponds to a quasi-cyclic LDPC with lifting Z=3. The original graph 200-a from which three copies were made is referred to herein as the base graph. To obtain graphs of different sizes, a “copy and permute” operation can be applied to the base graph. A corresponding PCM of the lifted graph can be constructed from the PCM of the base graph by replacing each entry in the base PCM with a Z×Z matrix. The 0 entries (those having no base edges) are replaced with the 0 matrix and the 1 entries (indicating a base edge) are replaced with a Z×Z permutation matrix. In the case of cyclic liftings, the permutations are cyclic permutations. FIG. 4 illustrates an example of an integer representation of a PCM 400 in accordance with various aspects of the present disclosure. The sub-block 405 shown in FIG. 4 shows a shifted identity matrix for an entry in the base PCM. (¶ [0056]). Communications manager 1015 may encode a set of information bits using a lifted LDPC code for a lifting size value Z from a base graph, the lifted LDPC code having a set of variable nodes corresponding to one or more information bits and parity bits and a set of check nodes, to generate an encoded bit stream. (¶ [0082]).
Even though Soriaga et al. discloses similar terminology as claim 1, it fails to teach, singly or in combination, perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein the base graph comprises one or more punctured variable nodes. As such, modification of the prior art of record to include the claimed perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein the base graph comprises one or more punctured variable nodes can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art at the time of the invention would have made the necessary modifications to the prior art of record to encompass the perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein the base graph comprises one or more punctured variable nodes set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein the base graph comprises one or more punctured variable nodes as set forth in claim 1. Independent claim 23 recite(s) a method with similar patentable features and are/is allowable for the same reasons as claim 1.
The claimed invention as set forth in claim 14 recites features such as:
A receiving device, comprising:
one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the receiving device to:
receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code;
generate the low-density parity-check code according to a lifted graph comprising multiple connected copies of a base graph based at least in part on a lifting procedure, the base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein the base graph comprises one or more punctured variable nodes; and
decode the plurality of information bits based at least in part on the plurality of parity bits, a plurality of information nodes, and a plurality of parity nodes, the plurality of information nodes and the plurality of parity nodes corresponding to the base graph.
The prior arts of record, namely Soriaga et al. (US-20190052400), teach A received LDPC codeword can be decoded to produce a reconstructed version of the original codeword. In the absence of errors, or in the case of correctable errors, decoding can be used to recover the original data unit that was encoded. Redundant bits may be used by decoders to detect and correct bit errors. LDPC decoders generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may be repeated several times. For example, each variable node 210 in the graph 200-a may initially be provided with a “soft bit” (e.g., representing the received bit of the codeword) that indicates an estimate of the associated bit's value as determined by observations from the communications channel. Using these soft bits the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel. (¶ [0053]).
The prior arts of record, however, fail to teach, singly or in combination, receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code and generate the low-density parity-check code according to a lifted graph comprising multiple connected copies of a base graph based at least in part on a lifting procedure, the base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein the base graph comprises one or more punctured variable nodes. As such, modification of the prior art of record to include the claimed receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code and generate the low-density parity-check code according to a lifted graph comprising multiple connected copies of a base graph based at least in part on a lifting procedure, the base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein the base graph comprises one or more punctured variable nodes can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art at the time of the invention would have made the necessary modifications to the prior art of record to encompass the receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code and generate the low-density parity-check code according to a lifted graph comprising multiple connected copies of a base graph based at least in part on a lifting procedure, the base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein the base graph comprises one or more punctured variable nodes set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the receive a signal comprising a plurality of information bits and a plurality of parity bits corresponding to a low-density parity-check code and generate the low-density parity-check code according to a lifted graph comprising multiple connected copies of a base graph based at least in part on a lifting procedure, the base graph comprising a plurality of variable nodes and a plurality of check nodes, wherein the base graph comprises one or more punctured variable nodes as set forth in claim 14. Independent claim 30 recite(s) a method with similar patentable features and are/is allowable for the same reasons as claim 14.
Hence, claims 1-30 would be allowable over the prior arts of record.
The Examiner favors the allowance of claims 1-30. Any comments considered necessary by applicant must be submitted no later than the payment of the Issue Fee and, to avoid processing delays, should preferably accompany the Issue Fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. KUDEKAR et al. (US 20220224356 A1) teaches Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word. (Abstract).
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 08/21/2026
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