DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 7/10/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CN118198159A to Tong (machine translation relied upon herein).
Regarding claims 1-8, Tong teaches a solar cell comprising
A silicon substrate (p. 26 of translation: “the semiconductor substrate may be a substrate of any semiconductor material such as a silicon substrate”; p. 27: “In the back contact battery provided by the embodiment of the present invention, the semiconductor substrate is a P-type semiconductor substrate”) having a front surface and a back (“backlight”) surface (top p. 26), wherein the silicon substrate comprises a P-type region (one of 11 or 12 of Fig. 2, bottom p. 27, bottom p. 29) located on the back surface, an N-type region located on the back surface (the other of 12 or 11), and an isolation region (“interval region”) located between the P-type region and the N-type region
A first electrode disposed in the P-type region (“electrode structure” in text, only explicitly shown in Fig. 63, bottom p. 53 through top p. 54)
A second electrode disposed in the N-type region
An electrical connector (“conductive semiconductor structure” in the text, 13 of Figs. 3, 4) disposed in the isolation region and configured to electrically connect a part of the P-type region and a part of the N-type region.
Per claim 2, a resistance of the electrical connector is smaller than a resistance of the isolation region (13 is formed of a semiconductor, 103 is vacuum or air, or filled with insulator according to Fig. 63, middle p. 33 of translation) and the resistance of the electrical connector is equal to a resistance of the P-type region or the N-type region (see paragraph at top of p. 56 of translation, which confirms that the material of 13 is the same as that of 12; therefore both elements must necessarily have the same resistance).
Per claim 3, the electrical connector is made of the same material as the N-type region or the P-type region, and the electrical connector extends from the N-type region or the P-type region towards the isolation region (paragraph at top of p. 56 of translation).
Per claim 4, the silicon substrate comprises a plurality of P-type regions and a plurality of N-type regions (Fig. 2 shows how each substrate comprises distinct tree-shaped regions comprising portions 14, 15, each having one of the corresponding polarities), the plurality of P-type regions and the plurality of N-type regions being alternately arranged in a first direction (right to left direction of Fig. 2).
In a particular embodiment (of Fig. 58 or Fig. 59) each of the plurality of N-type regions or P-type regions (as noted by the shade of the particular element 14 in the Figs.) is electrically connected to a corresponding one of the plurality of P-type regions or N-type regions through the electrical connector at only one side of the N-type region or P-type region in the first direction (Fig. 58, for instance, shows that electrical connector is formed only on a “bottom” side of lighter element 14/”top” side of darker element 14, bottom of p. 52, top p. 53 of translation).
A reference disclosure can anticipate a claim even if the reference does not describe "the limitations arranged or combined as in the claim, if a person of skill in the art, reading the reference, would ‘at once envisage’ the claimed arrangement or combination." Kennametal, Inc. v. Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381, 114 USPQ2d 1250, 1254 (Fed. Cir. 2015), MPEP §2131.02.III.
Per claim 5, each of the plurality of P-type (N-type) regions (either the lighter or darker colored regions, according to the cited text) comprises a first (second) main grid region (15 of Fig. 2) extending in a second direction (up-down in the frame of Fig. 2) and a plurality of first (second) auxiliary grid regions (14) extending in the first direction, the plurality of first (second) auxiliary grid regions being arranged in the second direction, and the plurality of first (second) auxiliary grid regions being connected to the first (second) main grid region.
The first main grid regions of the plurality of P-type regions and the second main grid regions of the plurality of N-type regions are alternately arranged in the first direction, and the plurality of first auxiliary grid regions of each of the plurality of P-type regions and the plurality of second auxiliary grid regions of a corresponding one of the plurality of N-type regions are alternately arranged in the second direction. MPEP §2125.
Per claim 6, based on the embodiments as understood from the text, the electrical connector (13 of Figs. 58, 59) is located in the isolation region around the first auxiliary grid region or the second auxiliary grid region.
Per claim 7, each of the plurality of first auxiliary grid regions is connected to one of the plurality of second auxiliary grid regions adjacent to the first auxiliary grid region through the electrical connector (Ibid.).
Per claim 8, the first direction is perpendicular to the second direction. MPEP §2125.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0331314 to Li.
Regarding claims 1-3, Li teaches a solar cell (Figs. 1-3) comprising
A silicon substrate 100 having a front surface 112 and a back surface 111 (¶0071, 0074), wherein the silicon substrate comprises a P-type region 102 located on the back surface, an N-type region 101 located on the back surface (¶0070, 0080-0083), and an isolation region 103 located between the P-type region and the N-type region (¶0077, 0078)
A first electrode 152 disposed in the P-type region 102 (¶0079)
A second electrode 151 disposed in the N-type region 101
An electrical connector 110 disposed in the isolation region 103 and configured to electrically connect a part of the P-type region 102 and a part of the N-type region 101 (¶0105-0107).
Per claim 2, a resistance of the electrical connector 110 is smaller than a resistance of the isolation region 103 (110 is formed of a semiconductor, 103 is vacuum or air), the resistance of the electrical connector is equal to a resistance of the P-type region 102 (110 and 102 are made of the same material, and therefore must necessarily have equal resistance, ¶0115, 0116).
Per claim 3, the electrical connector 110 is made of the same material as the P-type region 102, and the electrical connector extends from the P-type regions towards the isolation region (Fig. 3, ¶0115, 0116).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong as applied to claim 4 above.
Regarding claims 9, Tong teaches the limitations of claim 4. Tong is very clearly concerned with the ratio of an area of the electrical connectors to an area of the isolation region (Figs. 3, 5 illustrate dimensions D1 and W of electrical connector 13, dimensions D1 and D2 which can be used to calculate an area of an isolation region, bottom of p. 38 through bottom p. 45 of the translation explicitly discuss these parameters as well as the “orthographic projection area” of 13, S1, compared to an area of the back surface S2) in order to reduce local heat concentration; also see discussion of Figs. 52-55 on p. 47-52). Therefore it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to optimize the claimed ratio in order to reduce local heat concentration.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The discovery of an optimum value of a known result effective variable, without producing any new or unexpected results, is within the ambit of a person of ordinary skill in the art. See In re Boesch, 205 USPQ 215 (CCPA 1980) (see MPEP § 2144.05, II.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2024/0313136.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan S Cannon whose telephone number is (571)270-7186. The examiner can normally be reached M-F, 8:30am-5:30pm PST.
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Ryan S. Cannon
Primary Examiner
Art Unit 1726
/RYAN S CANNON/ Primary Examiner, Art Unit 1726
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