CTNF 19/206,802 CTNF 86358 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status. Notice of Claim Interpretation Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action. Information Disclosure Statement The information disclosure statements (IDS) submitted on 13 May 2025 and 16 April 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Specification 07-29 AIA The disclosure is objected to because of the following informalities: “653” should be --663-- in paragraph 0059 . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claims 1-6, 11-16, and 21 are r ejected under 35 U.S.C. 102(a )(1) as being a nticipated b y H inrichs et al. (US 10,417,127). I n regards to claims 1 and 11, Hinrichs teaches a memory device comprising: a cache configured to make a cache-hit determination, in response to a read request from a host, the cache-hit determination determining whether the read request results in a hit to the cache (“At block 602, a first request (e.g., a fetch request) to access a first set of data in a first memory (e.g., L1 cache) may be received.”, Col. 11, lines 36-38; “Per block 606, actual hit/miss processing may be initiated (e.g., beginning a search for the first set of data in a directory).”, Col. 11, lines 44-46); a pre-request manager configured to provide a memory processing unit with a pre-request for performing at least one operation of operations for determining data corresponding to the read request before completion of the determination of whether the read request results in a hit in the cache, wherein the pre-request corresponds to the read request or is a copy of the read request (“Per block 608, a second request may be generated (e.g., by the request generation logic 201 of FIG. 2) and transmitted to a second memory (e.g., primary RAM) in order to access the first set of data from the second memory.”, Col. 11, lines 50-54; “Per block 610, the actual hit/miss processing may complete after it has been initiated at block 606 and after the transmission of the second request at block 608.”, Col. 11, lines 60-62); and the memory processing unit configured to perform the at least one operation in response to the reception of the pre-request (“Per block 608, a second request may be generated (e.g., by the request generation logic 201 of FIG. 2) and transmitted to a second memory (e.g., primary RAM) in order to access the first set of data from the second memory.”, Col. 11, lines 50-54), wherein, data obtained from a memory module through the memory processing unit based on the pre-request is returned to the host in a case of the cache-hit determination determining a cache miss has occurred (“If there is not a hit (e.g., there is a miss), then per block 620 the second request may be resumed and transferred from the buffer to the second memory in order to access the first set of data.”, Col. 12, lines 15-18), and data hit in the cache is returned to the host in a case of the cache-hit determination determining a cache hit (“Per block 624, in response to the hit, the first set of data is accessed from the first memory to complete the first request.”, Col. 12, lines 26-28). In regards to claims 2 and 12, Hinrichs further teaches that the pre-request manager is configured to instruct the memory processing unit to abort an operation subsequent to the at least one operation in response to the cache-hit determination determining a cache hit for the read request (“Per block 614, if there was not an actual miss (e.g., there was a hit), the second request may be canceled since the first set of data was located in the first memory. Accordingly, any downstream processing by the second memory should be aborted.”, Col. 12, lines 1-5). In regards to claims 3 and 13, Hinrichs further teaches that the pre-request manager is configured to provide the memory processing unit with a read request comprising an abort flag value in response to the cache-hit determination of a cache hit determining a cache hit for the read request (“Accordingly, if there is a high likelihood that a current cache level has the needed data (a hit), then there is a high likelihood that the request_cancel 205 (to cancel the request 203) will be sent because the data was already located in the current level of cache analyzed and another request for the data in another level of cache/memory is not warranted.”, Col. 5, lines 34-40), and the memory processing unit is configured to remove a response corresponding to the read request comprising the abort flag value without subsequent processing of the response to the read request comprising the abort flag value in a memory response queue (“Per block 614, if there was not an actual miss (e.g., there was a hit), the second request may be canceled since the first set of data was located in the first memory. Accordingly, any downstream processing by the second memory should be aborted.”, Col. 12, lines 1-5). In regards to claims 4 and 14, Hinrichs further teaches that the pre-request manager is configured to notify the memory processing unit of aborting of the read request in response to the cache-hit determination determining a cache hit for the read request (“Accordingly, if there is a high likelihood that a current cache level has the needed data (a hit), then there is a high likelihood that the request_cancel 205 (to cancel the request 203) will be sent because the data was already located in the current level of cache analyzed and another request for the data in another level of cache/memory is not warranted.”, Col. 5, lines 34-40), and the memory processing unit is configured to remove the read request from a memory request queue or to deactivate the read request in the memory request queue (“Once the directory lookup 314 confirms that there is a L2 hit, the request_valid_late request 318 may be cleared from the request buffer 313 by the request_cancel 305 operation, so the request will not be processed downstream.”, Col. 7, lines 8-12). In regards to claims 5 and 15, Hinrichs further teaches that the memory processing unit is configured to perform an operation subsequent to the at least one operation in response to the cache-hit determination determining a cache miss for the read request (“Continuing with this example, if there is an actual cache miss at the current level of cache being analyzed and the first set of data is not exclusive, then per block 520, the second request at the second cache may continue to be executed, as the request was initiated at block 508.”, Col. 10, lines 47-51). In regards to claims 6 and 16, Hinrichs further teaches that the at least one operation comprises a data loading operation corresponding to the read request, the data loading operation loading data from the memory module (“Per block 608, a second request may be generated (e.g., by the request generation logic 201 of FIG. 2) and transmitted to a second memory (e.g., primary RAM) in order to access the first set of data from the second memory.”, Col. 11, lines 50-54), and the memory processing unit is configured to start the data loading operation (“Per block 608, a second request may be generated (e.g., by the request generation logic 201 of FIG. 2) and transmitted to a second memory (e.g., primary RAM) in order to access the first set of data from the second memory.”, Col. 11, lines 50-54) before the cache-hit determination is completed (“Per block 610, the actual hit/miss processing may complete after it has been initiated at block 606 and after the transmission of the second request at block 608.”, Col. 11, lines 60-62). In regards to claim 21, Hinrichs teaches a method performed by a compressed memory device comprising a cache and a memory module storing compressed data, the method comprising: receiving, from a host, a read request for data (“At block 602, a first request (e.g., a fetch request) to access a first set of data in a first memory (e.g., L1 cache) may be received.”, Col. 11, lines 36-38), the read request comprising a host address (“The request generation logic 201 sends out a request 203 (e.g., a fetch request), along with metadata of the request 203—i.e., request_info 202. For example, the request_info 202 can include the address of the data to be fetched.”, Col. 5, lines 21-25); based on the read request, making a determination that a cache-hit occurs for the host address in the cache (“Per block 610, the actual hit/miss processing may complete after it has been initiated at block 606 and after the transmission of the second request at block 608.”, Col. 11, lines 60-62); based on receiving the read request, and before the determining of the cache-hit is completed, initiating operations to retrieve the data from memory module (“Per block 608, a second request may be generated (e.g., by the request generation logic 201 of FIG. 2) and transmitted to a second memory (e.g., primary RAM) in order to access the first set of data from the second memory.”, Col. 11, lines 50-54; “Per block 610, the actual hit/miss processing may complete after it has been initiated at block 606 and after the transmission of the second request at block 608.”, Col. 11, lines 60-62); and based on the determining that the cache-hit occurred, aborting or not completing the operations to retrieve the data from the memory module (“Per block 614, if there was not an actual miss (e.g., there was a hit), the second request may be canceled since the first set of data was located in the first memory. Accordingly, any downstream processing by the second memory should be aborted.”, Col. 12, lines 1-5) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hinrichs et al. (US 10,417,127) in view of Valsan et al. (“Addressing isolation challenges of non-blocking caches for multicore real-time systems”) . In regards to claims 7 and 17, Hinrichs further teaches that the memory processing unit is configured to: in response to the cache-hit determination determining a cache miss for the read request, obtain data to be returned to the host based on data loaded from the memory module (“If there is not a hit (e.g., there is a miss), then per block 620 the second request may be resumed and transferred from the buffer to the second memory in order to access the first set of data.”, Col. 12, lines 15-18). Hinrichs fails to teach that the memory processing unit is configured to: receive the data corresponding to the read request from the memory module before the cache-hit determination is completed. Valsan teaches that the memory processing unit is configured to: receive the data corresponding to the read request from the memory module before the cache-hit determination is completed (“Multiple misses to the same cache-line are merged and notified together by a single MSHR entry. The MSHR entry is cleared when the corresponding memory request is serviced from the lower-level memory hierarchy.”; section 2.1, paragraph 3) which “can hide cache-miss penalties and therefore improves performance” (section 2.1, paragraph 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hinrichs with Valsan such that the memory processing unit is configured to: receive the data corresponding to the read request from the memory module before the cache-hit determination is completed which “can hide cache-miss penalties and therefore improves performance” ( id .) . 07-21-aia AIA Claim s 8-10, 18-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hinrichs et al. (US 10,417,127) in view of Shen et al. ( Modern Processor Design ) . In regards to claims 8 and 18, Hinrichs teaches claims 8 and 18. Hinrichs fails to teach that the at least one operation comprises an address translation operation for the read request, and the memory processing unit is configured to start the address translation operation for the read request before the cache-hit determination is completed. Shen teaches that the at least one operation comprises an address translation operation for the read request (“Instead of directly accessing the main memory with the address generated by the processor, the virtual address generated by the processor must first be translated into a physical address. The physical address is then used to access the physical main memory, as shown in Figure 4-35.”, page 189, paragraph 1), and the memory processing unit is configured to start the address translation operation for the read request before the cache-hit determination is completed (“At the same time as the page offset bits are being used to access the data cache, the remaining bits of the virtual address, i.e., the virtual page number, are used to access the TLB. Assuming the TLB and data cache access latencies are comparable, at the time when the physical page number from the TLB becomes available, the tag field (also containing the physical page number) of the data cache will also be available. The two p-bit physical page numbers can then be compared to determine whether there is a hit (matching physical page numbers) in the data cache or not.”, page 194, paragraph 1) “to reduce the overall latency” (page 194, paragraph 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hinrichs with Shen such that the at least one operation comprises an address translation operation for the read request, and the memory processing unit is configured to start the address translation operation for the read request before the cache-hit determination is completed “to reduce the overall latency” ( id .). In regards to claims 9 and 19, Hinrichs further teaches that the memory processing unit is configured to: in response to the cache-hit determination determining a cache miss for the read request, load data from the memory module and obtain data to be returned to the host using the loaded data (“If there is not a hit (e.g., there is a miss), then per block 620 the second request may be resumed and transferred from the buffer to the second memory in order to access the first set of data.”, Col. 12, lines 15-18). Hinrichs fails to teach that the memory processing unit is configured to: perform translation of an address corresponding to the read request before the cache-hit determination is completed; and load data from the memory module using the translated address. Shen teaches that the memory processing unit is configured to: perform translation of an address corresponding to the read request before the cache-hit determination is completed (“At the same time as the page offset bits are being used to access the data cache, the remaining bits of the virtual address, i.e., the virtual page number, are used to access the TLB. Assuming the TLB and data cache access latencies are comparable, at the time when the physical page number from the TLB becomes available, the tag field (also containing the physical page number) of the data cache will also be available. The two p-bit physical page numbers can then be compared to determine whether there is a hit (matching physical page numbers) in the data cache or not.”, page 194, paragraph 1); and load data from the memory module using the translated address (“Instead of directly accessing the main memory with the address generated by the processor, the virtual address generated by the processor must first be translated into a physical address. The physical address is then used to access the physical main memory, as shown in Figure 4-35.”, page 189, paragraph 1) “to reduce the overall latency” (page 194, paragraph 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hinrichs with Shen such that the memory processing unit is configured to: perform translation of an address corresponding to the read request before the cache-hit determination is completed; and load data from the memory module using the translated address “to reduce the overall latency” ( id .). In regards to claims 10 and 20, Hinrichs teaches claims 1 and 11. Hinrichs fails to teach that the memory device is configured to update data, which is to be returned to the host, into the cache, in response to the cache-hit determination determining a cache miss for the read request. Shen teaches that the memory device is configured to update data, which is to be returned to the host, into the cache, in response to the cache-hit determination determining a cache miss for the read request (“With a data cache, it is possible that the data being loaded are not resident in the data cache. This will result in a data cache miss and require the filling of the data cache from the main memory.”, page 185, paragraph 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hinrichs with Shen such that the memory device is configured to update data, which is to be returned to the host, into the cache, in response to the cache-hit determination determining a cache miss for the read request in order to reduce the access latency for subsequent accesses to that data. In regards to claim 22, Shen further teaches that the operations include translating the host address to a memory address in the memory module (“Instead of directly accessing the main memory with the address generated by the processor, the virtual address generated by the processor must first be translated into a physical address. The physical address is then used to access the physical main memory, as shown in Figure 4-35.”, page 189, paragraph 1) . 07-21-aia AIA Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hinrichs et al. (US 10,417,127) in view of Shen et al. (Modern Processor Design) and Ramakrishnan (US 2005/0114601) . In regards to claim 23, Hinrichs in view of Shen teaches claim 18. Hinrichs in view of Shen fails to teach that the operations include decompressing the requested data from the memory module. Ramakrishnan teaches that the operations include decompressing the requested data from the memory module (“Consequently, the compressed memory location designated by the pointer is accessed and the data is forwarded to the decompression engine 128. Subsequently, the decompressed data is output from the decompression engine 128 and is forwarded to the requester of the initial memory access of the incoming address.”, paragraph 0023) thereby “reducing large memory requirements” (paragraph 0004). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hinrichs with Shen and Ramakrishnan such that the operations include decompressing the requested data from the memory module thereby “reducing large memory requirements” ( id .) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Genduso (US 5,778,422) teaches that the L2 cache and memory controller each begin a processor memory read cycle simultaneously. Fertig (US 2009/0024835) teaches issuing a prefetch request before notification of a cache miss. O (US 2017/0206028) teaches determining a cache hit or miss on a memory module. Al Sheikh (US 2019/0065384) teaches issuing a demand read before determining a cache miss. Confalonieri (US 2023/0418756) teaches performing both cache look-up and bypass read operations . Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nathan Sadler/Primary Examiner, Art Unit 2139 15 June 2026 Application/Control Number: 19/206,802 Page 2 Art Unit: 2139 Application/Control Number: 19/206,802 Page 3 Art Unit: 2139 Application/Control Number: 19/206,802 Page 4 Art Unit: 2139 Application/Control Number: 19/206,802 Page 5 Art Unit: 2139 Application/Control Number: 19/206,802 Page 6 Art Unit: 2139 Application/Control Number: 19/206,802 Page 7 Art Unit: 2139 Application/Control Number: 19/206,802 Page 8 Art Unit: 2139 Application/Control Number: 19/206,802 Page 9 Art Unit: 2139 Application/Control Number: 19/206,802 Page 10 Art Unit: 2139 Application/Control Number: 19/206,802 Page 11 Art Unit: 2139 Application/Control Number: 19/206,802 Page 12 Art Unit: 2139 Application/Control Number: 19/206,802 Page 13 Art Unit: 2139 Application/Control Number: 19/206,802 Page 14 Art Unit: 2139 Application/Control Number: 19/206,802 Page 15 Art Unit: 2139
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