DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 10-11, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xuan et al. (US Patent Publication No. 20220114949; hereinafter Xuan).
With reference to claims 1, 11, and 20, an electronic device comprising a display device (Fig. 12) comprising: a display panel (see paragraph 206; Fig. 12) comprising a sub-pixel (see paragraph 92; Fig. 1) comprising:
a light-emitting element (Micro-LED) configured to receive a driving current, and to emit light (see paragraph 89, 92; Fig. 1);
a first transistor (M3) configured to generate the driving current (see paragraph 105, 111; Fig. 3);
a second transistor (M7) configured to transmit the driving current to the light-emitting element (Micro-LED) in response to a signal from a first node (N4) to which a control electrode of the second transistor is connected (illustrating control node of M7 connect to N4 via N2 and M5; see paragraphs 92, 97, 110; Fig. 3);
a third transistor (M4) configured to provide a first power voltage (Vef) to the first node (N4) in response to a signal from a second node (N2) (in teaching the switch circuit (7) is switchable between on and off in response to N2, thereby controlling voltage at N4; see paragraphs 99, 115; Fig. 3);
a fourth transistor (M3) configured to provide a data voltage (Vdata_T) to the second node (N2) (via N1 to C1) in response to a scan signal (Gate_T) (see paragraph 103, 108; Fig. 3); and
a first capacitor (C1) comprising a first electrode for receiving a ramp signa (ramp writing sub-circuit; 6), and a second electrode connected to the second node (N2).
With reference to claim 10, Xuan discloses the sub-pixel according to claim 1, and further disclose wherein the scan signal (Gate_T) has a waveform of a driving frequency (in teaching a first gate scan signal provided by the first gate line is at a high level; see paragraph 113; Figs. 3-4), and wherein the first power voltage (Vref) and the ramp signal (Ramp) have a waveform of a reference frequency (Vref) (see Fig. 4).
Allowable Subject Matter
Claims 2-9 and 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant is reminded of the indicated allowable subject matter as indicated. Further, definition of connections between circuitry elements should be recited as “directly connected” to clearly define the features of the invention in the claims.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CONG et al. (US2022/0343835) discloses a pixel circuit of a display device and a drive method, wherein the pixel circuit includes a light emitting device, a first thru third transistor, and a capacitor electrode for receiving a ramp signal (see paragraphs 69-71, 98-108; Figs. 1-2, 7).
YAMASHITA et al. (US20040207614) discloses a display drive method wherein each pixel comprises an EL display element, a drive transistor, a write transistor, and a capacitance electrode connected to a ramp voltage supply line (see paragraphs 90-123; Figs. 1-9).
Conclusion
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/ADE/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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