DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/13/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng (US Patent Publication No. 2023/0419902).
With reference to claims 1, 11, and 20, Cheng discloses an electronic device comprising a display device (see paragraph 50) comprising:
a display panel comprising a sub-pixel (10) (see paragraphs 50-51); and
a display panel driver configured to drive the display panel (see paragraph 50), wherein the sub-pixel (10) comprises:
a light-emitting element (EL) configured to receive a driving current, and to emit light (see paragraphs 57, 66; Fig. 2);
a first transistor (T4) configured to generate the driving current (Vref) (see paragraphs 57, 66, Fig. 2);
a second transistor (T8) configured to transmit the driving current to the light-emitting element (EL) in response to a signal from a first node (nda) (see paragraph 57, 66, Fig. 2);
a third transistor (T3) configured to provide a first power voltage to the first node (nda) in response to a signal from a second node (ndc) (see paragraphs 64-65; Fig.2);
a fourth transistor (T1) configured to provide a data voltage to the second node (ndc) in response to a scan signal (see paragraphs 64-65; Fig.2); and
a first capacitor (C1) comprising a first electrode for receiving a ramp signal (Vramp) (see paragraphs 61), and a second electrode connected to the second node (ndc) (see paragraph 59; Fig. 2).
Allowable Subject Matter
Claims 2-10 and 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CONG et al. (US2022/0343835) discloses a pixel circuit of a display device and a drive method, wherein the pixel circuit includes a light emitting device, a first thru third transistor, and a capacitor electrode for receiving a ramp signal (see paragraphs 69-71, 98-108; Figs. 1-2, 7).
YAMASHITA et al. (US20040207614) discloses a display drive method wherein each pixel comprises an EL display element, a drive transistor, a write transistor, and a capacitance electrode connected to a ramp voltage supply line (see paragraphs 90-123; Figs. 1-9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALECIA DIANE ENGLISH whose telephone number is (571)270-1595. The examiner can normally be reached M0n.-Fri. 7:00am-3:00am.
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/ADE/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625