Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-12, 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (2022/0302203) hereinafter, Lee in view of WO202110983 published 5/27/2021, Examiner is using Lee et al 2023/0005962 hereinafter, Lee2 as a translation.
In regards to claim 1, Lee teaches a display device, comprising:
a substrate (fig. 4 (11/12));
an active area in which a plurality of sub pixels is defined [0057] (fig. 2 active area);
PNG
media_image1.png
626
624
media_image1.png
Greyscale
a non-active area which is outside of the active area [0057] (fig. 9 NDA));
PNG
media_image2.png
528
608
media_image2.png
Greyscale
a light shielding layer on the substrate (fig. 6 BML on 11));
PNG
media_image3.png
600
864
media_image3.png
Greyscale
a transistor which is disposed on the light shielding layer [0082] and includes an active layer, a gate electrode, a source electrode, and a drain electrode [0081-0083];
[0083] The first transistor T1 may be disposed on the buffer layer BF, and may constitute a pixel circuit of each of the plurality of pixels. For example, the first transistor T1 may be a switching transistor or a driving transistor of the pixel circuit. The first transistor T1 may include an active layer ACT, a gate electrode G1, a source electrode SE, and a drain electrode DE. The active layer ACT may include a plurality of conductive regions ACTa and ACTb and a channel region ACTc therebetween.
an organic layer [0082] on the light shielding layer [127] metal;
a plurality of reflection plates on the organic layer; [149] electrodes 21 and 22 function as a light reflected from light emitting element;
Lee fails to teach an adhesive layer on the plurality of reflection plates;
However, Lee2 teaches an adhesive layer on the plurality of reflection plates (fig. 6 (115).
[0058] An adhesive layer 115 is disposed on the reflective layer 143. The adhesive layer 115 is an adhesive layer 115 for bonding the LED 130 on the reflective layer 143, and may insulate the reflective layer 143 formed of a metallic material from the LED 130. The adhesive layer 115 may be formed of a heat-curable material or a light-curable material, but is not limited thereto.
PNG
media_image4.png
656
814
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art to modify the teachings of Lee to further include an adhesive layer on the plurality of reflection plates as taught by Lee2 to bond the LED as taught by Lee2 [0058]. Examiner notes Lee using PAS1 as an insulating layer and well as Lee2 says about the adhesive layer.
Therefore, Lee in view of Lee2 teaches
a plurality of light emitting diodes on the adhesive layer (fig. 6 (130) Lee2);
a first planarization layer which is disposed on the adhesive layer and surrounds at least a portion of the plurality of light emitting diodes (fig. 4 (19 [0086-0089]) Lee (fig. 6 (116) Lee2);
a second planarization layer which is disposed on the first planarization layer and surrounds at least a portion of the plurality of light emitting diodes;(fig. 4 (41)) Lee and (fig. 6 (117)) Lee2) Examiner suggests clarification of planarization layers labeling to be closer in line with the specification and fig. 5.
a bank disposed [0089] Lee and (fig. 6 (119) Lee2) on the first planarization layer and formed of black material [0090] Lee,
wherein the plurality of light emitting diodes includes a pair of light emitting diodes configured to emit a same color and is disposed in each of the plurality of sub pixels (fig. 1 (131R and 132R) Lee2).
PNG
media_image5.png
488
584
media_image5.png
Greyscale
In regards to claim 2, Lee in view of Lee2 teaches the display device according to claim 1, wherein each of the plurality of light emitting diodes includes a first electrode and a second electrode disposed in a position higher than the first electrode (fig. 3 137 and 136) Lee2.
In regards to claim 3, Lee in view of Lee2 teaches display device according to claim 2, wherein the first electrode is electrically connected to the plurality of reflection plates through a contact hole [0067] Lee2 in view of [149] electrodes 21 and 22 Lee.
In regards to claim 7, Lee in view of Lee2 teaches display device according to claim 1, further comprising: a first connection electrode disposed on the second planarization layer and connected to a second electrode, wherein each of the plurality of light emitting diodes includes the second electrode which is electrically connected to the first connection electrode through a contact hole of the second planarization layer.(fig. 6 CNE1 and CNE2)[147] Lee
In regards to claim 8, Lee in view of Lee2 teaches display device according to claim 1, further comprising: a plurality of first pad electrodes which is disposed in the non-active area on a front surface of the substrate to transmit electrical signals to the plurality of sub pixels; a plurality of second pad electrodes which is disposed in the non-active area on a rear surface of the substrate to be electrically connected to a printed circuit board; and a plurality of side lines which is disposed on the front surface, the rear surface, and a side surface of the substrate to electrically connect the plurality of first pad electrodes and the plurality of second pad electrodes (fig. 2 and fig. 8 pads) Lee in view of fig. 3 180b) Lee2).
In regards to claim 9, Lee in view of Lee2 teaches display device according to claim 1, wherein the first planarization layer has a step. (fig. 6 19 step) Lee and (fig. 3 116 and step)[0051] Lee2
In regards to claim 10, Lee in view of Lee2 teaches display device according to claim 9, wherein a thickness of a part of the first planarization layer, which is adjacent to the plurality of light emitting diodes, is smaller than a thickness of a rest of the first planarization layer (fig. 6 19 step thinner around VL2) Lee and (fig. 3 116 and step) Lee2.
In regards to claim 11, Lee in view of Lee2 teaches display device according to claim 10, wherein the bank is disposed on both a first part of the first planarization layer and a second part of the first planarization layer, and wherein the first part has a smaller thickness than the second part.(fig. 6 below BP 19 and 17 and 19 is thinner above VL1) Lee
In regards to claim 12, Lee in view of Lee2 teaches display device according to claim 11, wherein an end of the bank and an end of the second planarization layer are disposed on the first part of the first planarization layer which has a smaller thickness than the second part of the first planarization layer, and wherein the end of the bank and the end of the second planarization layer are spaced apart from each other. (fig. 6 below BP 19 and 17 and 19 is thinner above VL1 at the end) Lee
In regards to claim 16, Lee in view of Lee2 teaches display device according to claim 1, further comprising: a capacitor which is disposed on the active layer and includes a first capacitor electrode and a second capacitor electrode on the first capacitor electrode to overlap the first capacitor electrode (fig. 6 CSE1 and CSE2) Lee.
In regards to claim 17, Lee in view of Lee2 teaches display device according to claim 16, wherein the first capacitor electrode and the gate electrode are disposed on a same layer and formed of a same material.(fig 6 G1 and CSE1) [134] Lee
In regards to claim 18, Lee in view of Lee2 teaches display device according to claim 17, wherein the first capacitor electrode is integrally formed with the gate electrode. (fig 6 G1 and CSE1) [134] Lee
In regards to claim 19, Lee in view of Lee2 teaches display device according to claim 1, wherein the plurality of reflection plates is connected to the transistor, and the plurality of light emitting diodes is connected to the transistor through the plurality of reflection plates. [149] electrodes 21 and 22 Lee
Allowable Subject Matter
Claims 4-6, 13-15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRANT SITTA whose telephone number is (571)270-1542. The examiner can normally be reached M-F 7:30-4:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-6084. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRANT SITTA/Primary Examiner, Art Unit 2622
Prosecution Insights