DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 4/6/2021. It is noted, however, that applicant has not filed a certified copy of the KR10-2021-0044773 application as required by 37 CFR 1.55.
Claim Objections
Claims 1 and 2 objected to because of the following informalities: the claims recite “its DMA capabilities” which should be --the DMA capabilities--. Appropriate correction is required.
Claim 18 recites “to enhance efficiency of burst transfers” which is an intended use recitation and should be changed to --during burst transfers--. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: the claims recite “both weight parameters and activation data” which should be --the weight parameters and the activation data--. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 15-16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts (US 2021/0049100 A1) hereinafter Roberts in view of Che et al. (US 2020/0249998 A1) hereinafter Che et al. in further view of Baluja et al. (US 2021/0209475 A1) hereinafter Baluja et al.
Regarding claim 1, Roberts teaches a system for artificial neural network (ANN) processing, the system comprising:
a Neural Processing Unit (NPU) configured to execute an ANN model (a memory controller having a neural network block that implements machine learning techniques Paragraphs [0143]), said NPU being configured to process ANN model data according to a sequence of operations derived from said ANN model (a memory controller having a neural network block performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8);
a plurality of Dynamic Random-Access Memory (DRAM) chips providing a memory dedicated to said artificial neural network, said plurality of DRAM chips being configured to store said ANN model data (one or more DRAM memory arrays 28 acts as a cache and/or pre-fetch buffer for the system Paragraph [0084], [0089]), wherein said ANN model data (input parameters 130 are supplied to the neural network block during a cycle of its neural network Paragraph [0145]); and
a memory controller operatively coupled to said NPU and said plurality of DRAM chips (Fig. 5 depicts a memory controller coupled to machine learning block 114 and memory devices 18A),
wherein said memory controller is configured to control access to said ANN model data within said plurality of DRAM chips by generating memory control signals for read and write operations based at least in part on said sequence of operations (the memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage Paragraph [0092]).
Roberts does not appear to explicitly teach, however, Che et al. further teaches a memory controller operatively coupled to said NPU and said plurality of memory chips (memory controller 106 along with DMA unit 108 is included as part of NPU architecture Paragraph [0016]), said memory controller including Direct Memory Access (DMA) capabilities (DMA unit can assist with transferring data via direct memory access Paragraphs [0022], [0016]); wherein said memory controller, through its DMA capabilities, is configured to control access to said ANN model data (memory controller can manage the read/write data via the DMA unit Paragraphs [0020]-[0022]).
The disclosures of Roberts and Che et al., hereinafter RC, are analogous art to the claimed invention because they are in the same field of endeavor of neural network processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of RC before them, to modify the teachings of Roberts to include the teachings of Che et al. since both RC teach processing data for a neural network. Therefore it is applying a known technique (a memory controller with direct memory access capabilities to control access to data [0020]-[0022] of Che et al.) to a known device (a neural network processing system for predicting future data accesses of Roberts et al.) ready for improvement to yield predictable results (a memory controller and its DMA unit coupled to the NPU can perform direct memory access), KSR, MPEP 2143.
RC does not appear to explicitly teach, however, Baluja et al. further teaches wherein said ANN model data includes weight parameters and activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]).
The disclosures of RC and Baluja et al., hereinafter RCB, are analogous art to the claimed invention because they are in the same field of neural networks. Because both RCB teach the use of training neural network models with data (ex. general input parameters of Roberts), it would have been obvious to one skilled in the art to substitute one type of data for another to achieve the predictable result of training neural networks utilizing a particular type of data as disclosed by Baluja et al., this case, input parameters associated with weight and activation values (KSR, MPEP 2143).
Regarding claim 2, RCB teaches all of the features with respect to claim 1 as outlined above.
Che et al. further teaches wherein said sequence of operations is determined by a compiler at compilation time of said ANN model and utilized by said NPU for processing and by said memory controller to direct its DMA capabilities (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028]).
Regarding claim 3, RCB teaches all of the features with respect to claim 1 as outlined above.
Roberts further teaches wherein said memory controller is an Artificial Neural Network Memory Controller (AMC) (memory controller utilizes a machine learning block that implements neural network techniques Paragraph [0131]).
Regarding claim 4, RCB teaches all of the features with respect to claim 1 as outlined above.
Che et al. further teaches wherein said NPU includes a scheduler that utilizes said sequence of operations to manage processing of said ANN model data (neural network processors comprise a compiler Paragraph [0027], wherein the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029]).
Regarding claim 6, RCB teaches all of the features with respect to claim 1 as outlined above.
Roberts further teaches wherein said memory controller analyzes memory access patterns to predict upcoming data requests and issues advance memory control signals for prefetching said ANN model data to refine access timing (the memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage Paragraph [0092], as memory access patterns are often cyclical, thus, the controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031].
Note that the limitation “to refine access timing” is an intended use limitation (i.e., describes an intended result or consequence of the prefetching) and is not given patentable weight. The only requirement on the claim is that prefetching can be performed which in itself would enable better access timing).
Regarding claim 15, Roberts teaches a system for artificial neural network (ANN) processing, the system comprising:
a Neural Processing Unit (NPU) configured to process an ANN model (a memory controller having a neural network block that implements machine learning techniques Paragraphs [0143]);
a memory comprising a plurality of Dynamic Random-Access Memory (DRAM) chips dedicated to artificial neural network operations (one or more DRAM memory arrays 28 acts as a cache and/or pre-fetch buffer for the system Paragraph [0084], [0089]), said memory configured to store ANN model data (input parameters 130 are supplied to the neural network block during a cycle of its neural network Paragraph [0145]); and
a memory controller operatively coupled to said NPU and said memory (Fig. 5 depicts a memory controller coupled to machine learning block 114 and memory devices 18A);
wherein said memory controller generates memory control signals for said memory to access said ANN model data in accordance with a sequence of operations (the memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage Paragraph [0092]), said sequence being related to processing of said ANN model (a memory controller performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8).
Roberts does not appear to explicitly teach, however, Che et al. further teaches said sequence determined at least in part by a compiler (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028]).
The disclosures of Roberts and Che et al., hereinafter RC, are analogous art to the claimed invention because they are in the same field of endeavor of neural network processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of RC before them, to modify the teachings of Roberts to include the teachings of Che et al. since both RC teach processing data for a neural network. Therefore it is applying a known technique (the sequence being determined at least in part by a compiler [0028]-[0029] of Che et al.) to a known device (a neural network processing system for predicting future data accesses of Roberts et al.) ready for improvement to yield predictable results (the compiler having a scheduler helps in determining the sequence), KSR, MPEP 2143.
RC does not appear to explicitly teach, however, Baluja et al. further teaches the ANN model data including weight parameters and activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]).
The disclosures of RC and Baluja et al., hereinafter RCB, are analogous art to the claimed invention because they are in the same field of neural networks. Because both RCB teach the use of training neural network models with data (ex. general input parameters of Roberts), it would have been obvious to one skilled in the art to substitute one type of data for another to achieve the predictable result of training neural networks utilizing a particular type of data as disclosed by Baluja et al., this case, input parameters associated with weight and activation values (KSR, MPEP 2143).
Regarding claim 16, RCB teaches all of the features with respect to claim 15 as outlined above.
Roberts further teaches generates ANN data locality information defining said sequence of operations, said information detailing access to said data and being utilized by said memory controller, in coordination with said NPU, to identify data access patterns for prediction (a memory controller having a neural network block performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8. The controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031]) and Che et al. teaches wherein said compiler generates ANN data locality information defining said sequence of operations (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028]). Baluja et al. further teaches that the neural network data can be weight parameters and activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]).
Regarding claim 19, RCB teaches all of the features with respect to claim 15 as outlined above.
Che et al. further teaches wherein said sequence of operations, established through compilation, coordinates concurrent or sequential access by said NPU, via said memory controller, to said data (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028], wherein the subsets of data can all be performed in parallel Paragraph [0063]), wherein Baluja teaches the data can be weight parameters and said activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]).
Regarding claim 20, RCB teaches all of the features with respect to claim 15 as outlined above.
Roberts further teaches wherein said memory controller, using information from said NPU regarding the execution of said sequence, is configured to: analyze memory access patterns related to NPU operations for data to predict imminent data requirements; and issue advance memory access instructions to said plurality of DRAM chips based on said predictions, thereby achieving latency reduction (a memory controller having a neural network block performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8. The controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031]. Note that the limitation “thereby achieving latency reduction” is an intended use limitation (i.e., describes an intended result or consequence of the issuing) and is not given patentable weight. The only requirement on the claim is that issuing can be performed which in itself would reduce latency), wherein Baluja teaches the data can be weight parameters and said activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]). Che et al. teaches wherein said sequence can be said compiler-determined sequence (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028]).
Claim(s) 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over RCB in further view of Golov (US 2020/0082852 A1) hereinafter Golov.
Regarding claim 5, RCB teaches all of the features with respect to claim 1 as outlined above.
Roberts further teaches wherein said memory control signals generated by said memory controller specify memory addresses distributed across said plurality of DRAM chips (the memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage by specifying memory addresses associated with the access requests Paragraph [0092], [0057]).
RCB does not appear to explicitly teach, however, Golov teaches said memory control signals generated by said memory controller specify operation types, including burst transfer modes (one or more banks can be operated in a continuous burst mode Paragraph [0034], [0020]).
RCB and Golov both teach tree data neural network processing and/or using burst mode, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of RCB and Golov before the effective filing date of the invention, to modify the teachings of RCB by including operation types such as burst transfer mode, as taught by Golov.
One of ordinary skill in the art would have been motivated to include burst transfer mode to deliver its maximum data throughput which improves overall system performance throughput.
Regarding claim 17, RCB teaches all of the features with respect to claim 15 as outlined above.
Roberts further teaches wherein the generation of said memory control signals by said memory controller includes specifying parameters and initiating advance data access requests for predicted needs of weight parameters or activation data to reduce memory latency (a memory controller having a neural network block performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8. The controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031]. Note that the limitation “thereby achieving latency reduction” is an intended use limitation (i.e., describes an intended result or consequence of the issuing) and is not given patentable weight.) and Baluja teaches the data can be weight parameters and said activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]).
RCB does not appear to explicitly teach, however, Golov teaches said memory control signals generated by said memory controller further specify burst transfer parameters (one or more banks can be operated in a continuous burst mode Paragraph [0034], [0020]).
RCB and Golov both teach tree data neural network processing and/or using burst mode, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of RCB and Golov before the effective filing date of the invention, to modify the teachings of RCB by including operation types such as burst transfer mode, as taught by Golov.
One of ordinary skill in the art would have been motivated to include burst transfer mode to deliver its maximum data throughput which improves overall system performance throughput.
Claim(s) 8, 10, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts (US 2021/0049100 A1) hereinafter Roberts in view of Baluja et al. (US 2021/0209475 A1) hereinafter Baluja et al.
Regarding claim 8, Roberts teaches a system for artificial neural network (ANN) processing, the system comprising:
a plurality of Dynamic Random-Access Memory (DRAM) chips collectively forming a memory system dedicated to supporting artificial neural network computations (one or more DRAM memory arrays 28 acts as a cache and/or pre-fetch buffer for the system Paragraph [0084], [0089]), said DRAM chips configured to store ANN model data (input parameters 130 are supplied to the neural network block during a cycle of its neural network Paragraph [0145]);
a Neural Processing Unit (NPU) configured to execute an ANN model using said ANN model data (a memory controller having a neural network block that implements machine learning techniques Paragraphs [0143]); and
a memory controller operatively coupled to said NPU and said plurality of DRAM chips (Fig. 5 depicts a memory controller coupled to machine learning block 114 and memory devices 18A);
wherein said memory controller is configured to generate memory control signals to manage access to said ANN model data across said plurality of DRAM chips (the memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage Paragraph [0092]), said generation being based at least in part on a sequence of memory access operations related to said ANN model (a memory controller performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8).
Roberts does not appear to explicitly teach, however, Baluja et al. further teaches the ANN model data, including weight parameters and activation data (the device can include lookup tables that provides results values for pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]).
The disclosures of Roberts and Baluja et al., hereinafter RB, are analogous art to the claimed invention because they are in the same field of neural networks. Because both RB teach the use of training neural network models with data (ex. general input parameters of Roberts), it would have been obvious to one skilled in the art to substitute one type of data for another to achieve the predictable result of training neural networks utilizing a particular type of data as disclosed by Baluja et al., this case, input parameters associated with weight and activation values (KSR, MPEP 2143).
Regarding claim 10, RB teaches all of the features with respect to claim 8 as outlined above.
Roberts et al. further teaches wherein said memory controller is configured to receive memory access requests from said NPU related to ANN model execution, including requests for weight parameters and activation data (Baluja et al. teaches the neural network parameters can be pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]), and to process advance data access requests based on predictions (a memory controller having a neural network block performs memory access requests having a current memory access pattern Paragraphs [0211]-[0218], wherein the processing corresponds to neural network parameters Paragraph [0145], also see Fig. 8. The controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031]).
Regarding claim 12, RB teaches all of the features with respect to claim 8 as outlined above.
Roberts et al. further teaches wherein said NPU executes ANN models requiring access to different sets of weight parameters and activation data (Baluja et al. teaches the neural network parameters can be pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]), with said memory controller coordinating memory access for said NPU (the memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage Paragraph [0092]).
Regarding claim 13, RB teaches all of the features with respect to claim 8 as outlined above.
Roberts et al. further teaches wherein said memory controller generates said memory control signals, incorporating advance data access requests for anticipated needs of weight parameters or activation data (Baluja et al. teaches the neural network parameters can be pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]) based on pattern recognition and prediction by said NPU or said memory controller, to reduce processing latency (The controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031]. The memory controller helps determine data demanded (i.e., targeted) by the processing circuitry and outputs control signals that instruct the sub-system to adjust data storage Paragraph [0092]).
Claim(s) 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over RB in further view of Che et al. (US 2020/0249998 A1) hereinafter Che et al.
Regarding claim 9, RB teaches all of the features with respect to claim 8 as outlined above.
Roberts further teaches wherein said sequence of memory access operations coordinates the fetching of said weight parameters and said activation data (Baluja et al. teaches the neural network parameters can be pairs of activation values and weight values associated with the machine-learned models Paragraph [0071]) and further refined by said NPU or said memory controller predicting subsequent data accesses based on recognized patterns (The controller may predict subsequent access patterns based on memory access information associated with requests fulfilled prior to the subsequent access pattern Paragraph [0131] and preemptively (e.g., predictively) pre-fetch data to a lower memory Paragraph [0031]).
RB does not appear to explicitly teach, however, Che et al. teaches said sequence being determined based on data flow dependencies as analyzed by a compiler (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028]).
The disclosures of RB and Che et al., hereinafter RBC, are analogous art to the claimed invention because they are in the same field of endeavor of neural network processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of RBC before them, to modify the teachings of RB to include the teachings of Che et al. since both RB teach processing data for a neural network. Therefore it is applying a known technique (the sequence being determined at least in part by a compiler [0028]-[0029] of Che et al.) to a known device (a neural network processing system for predicting future data accesses of Roberts et al.) ready for improvement to yield predictable results (the compiler having a scheduler helps in determining the sequence), KSR, MPEP 2143.
Regarding claim 11, RB teaches all of the features with respect to claim 8 as outlined above.
RB does not appear to explicitly teach, however, Che et al. teaches wherein said weight parameters are distributed across said plurality of DRAM chips for parallel access under the coordination of said memory controller as guided by information from a compiler (the compiler includes a scheduler which is configured to schedule tasks with respect to execution order of operations is Paragraph [0029], and compilers also generates instructions that pushes commands to the NPU or instruct a DMA unit to load its instructions Paragraph [0028], wherein the subsets of data can all be performed in parallel Paragraph [0063]).
The disclosures of RB and Che et al., hereinafter RBC, are analogous art to the claimed invention because they are in the same field of endeavor of neural network processing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of RBC before them, to modify the teachings of RB to include the teachings of Che et al. since both RB teach processing data for a neural network. Therefore it is applying a known technique (the sequence being guided by a compiler [0028]-[0029] of Che et al.) to a known device (a neural network processing system for predicting future data accesses of Roberts et al.) ready for improvement to yield predictable results (the compiler having a scheduler helps in guiding the memory accesses), KSR, MPEP 2143.
Allowable Subject Matter
Claims 7, 14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, “wherein said compiler provides layout information for said ANN model data within said plurality of DRAM chips as part of said sequence of operations, said layout information being utilized by said memory controller to facilitate efficient prefetching and burst transfer modes,” is not taught by the prior art. The closest prior art is Roberts and Che et al. Roberts further teaches table entry information includes correlation parameter information, which is used to indicate a distance between a storage location targeted by the memory access request and a storage location targeted by a previous memory access request, which reads on the claimed layout information, which is used to improve data pre-fetching efficacy. Che et al. separately teaches the compiler includes a scheduler which schedules the tasks. However, the combination of Roberts and Che et al. does not teach the layout information that is used to facilitate pre-fetching and burst transfer mode is provided by the compiler.
Regarding claim 14, “wherein said memory controller organizes said activation data and said weight parameters within said plurality of DRAM chips in regions whose layouts are determined by their respective expected sizes and access characteristics, said organization planned during compilation,” is not taught by the prior art of record. The closest prior art is Roberts and Che et al. Roberts further teaches table entry information includes correlation parameter information, which is used to indicate a distance between a storage location targeted by the memory access request and a storage location targeted by a previous memory access request, which reads on the claimed layout information, which is used to improve data pre-fetching efficacy. Che et al. separately teaches the compiler includes a scheduler which schedules the tasks. However, the combination of Roberts and Che et al. does not teach organizing data whose layouts are determined by expected sizes and access characteristics.
Regarding claim 18, “wherein said memory controller is further configured to manage the arrangement of said weight parameters and said activation data across said plurality of DRAM chips in layouts based on their respective sizes and access patterns to enhance efficiency of burst transfers and advance data access requests,” is not taught by the prior art of record. The closest prior art is Roberts and Che et al. Roberts further teaches table entry information includes correlation parameter information, which is used to indicate a distance between a storage location targeted by the memory access request and a storage location targeted by a previous memory access request, which reads on the claimed layout information, which is used to advance data requests. Che et al. separately teaches the compiler includes a scheduler which schedules the tasks. However, the combination of Roberts and Che et al. does not teach managing weight parameters and activation data in layouts based on their sizes and access patterns.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Loh et al. (US 2021/0192337 A1) teaches an ANN model can be partitioned based on model parallelism such that the ANN model is divided into a sequence of partitions that can be running in parallel.
Shan et al. (US 2021/0089874 A1) teaches binarizing activation values and weight values in a convolutional neural network.
Lu et al. (US 2022/0399060 A1) teaches providing data output based on a previous access pattern during prefetch.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139
Prosecution Insights