Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Specification
The disclosure is objected to because of the following informalities: typographical error. “first reference voltage” in par 0035 line 18 should be “second reference voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-13, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (U.S. Patent Application 20240177679 A1, hereinafter “Park”).
Regarding Claim 1, Park teaches a method (par 0012 Fig 11 method) for displaying an image, comprising:
providing a display panel and a control circuit, wherein the control circuit is electrically connected to the display panel (par 0039 Fig 1 a display panel 110 electrically connected to a control circuit comprising a combination of timing controller 140 and power management circuit 150 is provided);
during a detection period (par 0239 Fig 10 during a sensing period), using the control circuit to provide a plurality of gate testing voltages to the display panel (par 0051 Fig 1 the timing controller 140 controls the operation of the gate driver 120; par 0120 Fig 6 the gate voltage line 131 applies the high-potential gate voltage GVDD and the low-potential gate voltage GVSS supplied from the power management circuit 150 to each of the first to kth stage circuits ST(1) to ST(k); par 0238 Fig 11 the timing controller controls the operation of the gate driver 120 to provide test gate voltages to the display panel which have values that decrease a predetermined amount from the initial set voltage so that the deterioration state of the gate driving circuit 120 may be identified), wherein the plurality of gate testing voltages comprise
a maximum testing voltage,
an operation voltage and
a failure testing voltage (par 0238 Fig 11 e.g., the initial set voltage of the test gate voltage may be set to], and the deterioration state of the gate driving circuit 120 may be identified while decreasing by 1V increments; par 0280 the sequentially lowered gate voltage at which an error is detected is set as the error gate voltage [failure testing voltage] = 4V in the par 0283 example; par 0282 Fig 11 S500 [the operation voltage] is set to a [any] voltage higher than the error gate voltage, e.g. in the example of par 0283 though 10V is set as the operation voltage in the example, an operation voltage of 5V is equally taught),
the maximum testing voltage is higher than the operation voltage (per the teachings of Park par 0283, [a maximum testing voltage 6V] is higher than the operation voltage 5V),
the operation voltage is higher than the failure testing voltage (per the teachings of Park par 0283, [the operation voltage 5V is higher than the failure testing voltage 4V), and
a time point at which the maximum testing voltage appears is earlier than a time point at which the failure testing voltage appears (such would be the case in the cited scenario of Park);
during a working period, using the control circuit to output at least one image signal to the display panel according to the operation voltage (par 0098 Fig 11 S600 the stable/ operation voltage is applied to the gate driving circuit 120 and par 0040 the display panel 110 displays an image based on a scan signal transferred from the gate driving circuit 120 through the plurality of gate lines GL).
Regarding Claim 2, Park teaches the method for displaying the image according to claim 1, wherein
a number of the operation voltage is two, and a time point at which the failure testing voltage appears is between time points at which the two operation voltages appear (such would be the case in the above cited scenario of Park Fig 11; i.e. steps of Vg of 6V, 5V, 4V, 5V would occur).
Regarding Claim 3, Park teaches the method for displaying the image according to claim 1, wherein
in the plurality of gate testing voltages, the maximum testing voltage is a first testing voltage, and the operation voltage is a last testing voltage (such would be the case in the above cited scenario of Park Fig 11; i.e. steps of Vg of 6V, 5V, 4V, 5V would occur).
Regarding Claim 8, Park teaches the method for displaying the image according to claim 1, wherein
after the control circuit provides the failure testing voltage, the control circuit is used to receive a failure signal (par 0280 Fig 12 after providing the failure testing voltage on the gate voltage, the control circuit at least timing controller 140 receives the digital value of Vsen representing a failure signal).
Regarding Claim 9, Park teaches the method for displaying the image according to claim 1, wherein
a maintenance time of each of the plurality of gate testing voltages is longer than or equal to a frame time (par 0252 Fig 11 the cycle of changing gate testing voltages and sensing repeats during a blank period between frames).
Regarding Claim 10, Park teaches the method for displaying the image according to claim 1, wherein
during the detection period, the control unit is used to provide the image signal that generates a black frame (par 0252 Fig 11 the cycle of changing gate testing voltages and sensing repeats during a blank period between frames; par 0226 he sensing period may correspond to a blank period in which the display panel 110 does not emit light).
Claim 11 presents the limitations of Claim 1 in a different claim category, and therefore Claim 11 is rejected with a rationale similar to Claim 1, mutatis mutandis.
Claim 12 presents the limitations of Claim 2 in a different claim category, and therefore Claim 12 is rejected with a rationale similar to Claim 2, mutatis mutandis.
Claim 13 presents the limitations of Claim 3 in a different claim category, and therefore Claim 13 is rejected with a rationale similar to Claim 3, mutatis mutandis.
Claim 18 presents the limitations of Claim 8 in a different claim category, and therefore Claim 18 is rejected with a rationale similar to Claim 8, mutatis mutandis.
Claim 19 presents the limitations of Claim 9 in a different claim category, and therefore Claim 19 is rejected with a rationale similar to Claim 9, mutatis mutandis.
Claim 20 presents the limitations of Claim 20 in a different claim category, and therefore Claim 20 is rejected with a rationale similar to Claim 20, mutatis mutandis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-7 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. Patent Application 20240177679 A1, hereinafter “Park”) in view of Wu et al. (U.S. Patent Application Publication 20200219439 A1, hereinafter “Wu”).
Regarding Claim 4, Park teaches the method for displaying the image according to claim 1. However, Park appears not to expressly teach wherein
the control circuit comprises a first lookup table and a second lookup table, wherein
the first lookup table corresponds to a first reference voltage,
the second lookup table corresponds to a second reference voltage, and
the first reference voltage is lower than the second reference voltage.
Wu teaches wherein
the control circuit (par 0059 Fig 4 processor 400) comprises a first lookup table and a second lookup table (par 0059 Fig 6 Wu teaches providing grayscale correlations to varying gate voltage in the form of a look-up table). wherein
the first lookup table corresponds to a first reference voltage (par 0024 teaches reducing the data to sets of several gate voltage values, of which a lower one might be defined as a first reference voltage),
the second lookup table corresponds to a second reference voltage (par 0024 teaches reducing the data to sets of several gate voltage values, of which a higher one might be defined as a second reference voltage), and
the first reference voltage is lower than the second reference voltage (par 0024 teaches reducing the data to sets of several gate voltage value, of which the such-defined first reference voltage is less than the such-defined second reference voltage).
Park and Wu are analogous art as they each pertain to display gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the method of Park with the inclusion of the provision of grayscale correlations to varying gate voltage in the form of a look-up table of Wu. The motivation would have been in order that the total number of grayscale values and the total number of gate voltages measured to determine the mapping correlation between grayscale values of a pixel as a function of voltages applied on its subpixels can be greatly reduced (Wu par 0024).
Regarding Claim 5, Park as modified teaches the method for displaying the image according to claim 4, wherein
during the working period, when the operation voltage is lower than or equal to the first reference voltage, the control circuit is used to generate the at least one image signal according to a parameter value of the first lookup table (Wu par 0024 when the operation voltage is equal to the first reference voltage, the control circuit is used to generate the at least one image signal according to a parameter value [grayscale values] of the first lookup table).
Park and Wu are analogous art as they each pertain to display gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the method of Park with the inclusion of the provision of grayscale correlations to varying gate voltage in the form of look-up tables of Wu. The motivation would have been in order that the total number of grayscale values and the total number of gate voltages measured to determine the mapping correlation between grayscale values of a pixel as a function of voltages applied on its subpixels can be greatly reduced (Wu par 0024).
Regarding Claim 6, Park as modified teaches the method for displaying the image according to claim 4, wherein
when the operation voltage is higher than or equal to the second reference voltage, the control circuit is used to generate the at least one image signal according to a parameter value of the second lookup table (Wu par 0024 when the operation voltage is equal to the second reference voltage, the control circuit is used to generate the at least one image signal according to a parameter value [grayscale values] of the second lookup table).
Park and Wu are analogous art as they each pertain to display gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the method of Park with the inclusion of the provision of grayscale correlations to varying gate voltage in the form of look-up tables of Wu. The motivation would have been in order that the total number of grayscale values and the total number of gate voltages measured to determine the mapping correlation between grayscale values of a pixel as a function of voltages applied on its subpixels can be greatly reduced (Wu par 0024).
Regarding Claim 7, Park as modified teaches the method for displaying the image according to claim 4, wherein
when the operation voltage is higher than the first reference voltage and lower than the second reference voltage, the control circuit is used to generate a parameter value using an interpolation method, and to generate at least one image signal according to the parameter value (Wu par 0024 teaches interpolation between tables to determine e.g. grayscale values for a gate voltage between two reference gate voltage tables).
Park and Wu are analogous art as they each pertain to display gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the method of Park with the inclusion of the provision of grayscale correlations to varying gate voltage in the form of a look-up table of Wu. The motivation would have been in order that the total number of grayscale values and the total number of gate voltages measured to determine the mapping correlation between grayscale values of a pixel as a function of voltages applied on its subpixels can be greatly reduced (Wu par 0024).
Claim 14 presents the limitations of Claim 4 in a different claim category, and therefore Claim 14 is rejected with a rationale similar to Claim 4, mutatis mutandis.
Claim 15 presents the limitations of Claim 5 in a different claim category, and therefore Claim 15 is rejected with a rationale similar to Claim 5, mutatis mutandis.
Claim 16 presents the limitations of Claim 6 in a different claim category, and therefore Claim 16 is rejected with a rationale similar to Claim 6, mutatis mutandis.
Claim 17 presents the limitations of Claim 7 in a different claim category, and therefore Claim 17 is rejected with a rationale similar to Claim 7, mutatis mutandis.
Conclusion
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/MARK EDWARDS/Primary Examiner, Art Unit 2624