DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: the acronyms “SDFFQ” and “SDFFQCBM” of ¶[4]-[5] have not been defined. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claims 1-20, it is unclear how “high phase” and “low phase” is to be interpreted in the claims. Examiner believes that all instances of “phase” in the claims are not referring to its conventional definition (a specific position of a wave relative to its repetitive cycle, e.g., 180 degrees). For the purposes of examination, Examiner will interpret “high phase of the clock signal” and “low phase of the clock signal” to be identical in scope to “when the clock signal is logic high” and “when the clock signal is logic low”, respectively.
For claims 1-20, the limitation “a transistor bridge circuit for sharing a clock signal between the master stage flip-flop and the slave stage flip-flop” is considered misdescriptive. Applicant’s Specification teaches that the transistor bridge circuit 406 comprises PMOS transistors P1, P2 and P3 [133]. The output of the transistor bridge circuit is pow1 and pow2 which are power supply nodes selectively enabled based on both data signals (X3, X4) and a clock signal (CK). Thus, the clock signal (CK) is not being shared (i.e. provided by) the transistor bridge circuit to the master stage flip-flop or the slave stage flip-flop since pow1 and pow2 are capable of being logic high (i.e., providing power) regardless of the state of the clock signal (when X3 or X4 are logic low, respectively).
For the purposes of examination, Examiner will interpret this limitation as being identical in scope to “a transistor bridge circuit for selectively providing power to the master stage flip-flop and the slave stage flip-flop based on a clock signal.”
Claims 1 and 16 (and by virtue of dependence, claims 2-15 and 17-19) recite “the buffered inverted data”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, Examiner will interpret the first instance of this term within claims 1 and 16 as “buffered inverted data.”
Claim 2 recites “the first internal feedback to the flip flop”. There is insufficient antecedent basis for “the first internal feedback” in the claim. Note that both the master stage and the slave stage provide internal feedback and two flip-flops have been defined within the flip-flop of claim 1 (a master stage flip-flop and a slave stage flip-flop). For the purposes of examination, Examiner will interpret this limitation as “the master stage internal feedback to the master stage flip-flop”
Claim 19 recites “wherein the slave feedback circuit provides a second internal feedback in the form of previous slave stage output during high phase of the clock signal, through the transistor bridge circuit with common clock transistor when the clock signal is low”. It cannot be understood what “previous” and “common” refer to (previous to what? common to what?) and how the transistor bridge circuit is used to carry out the claimed provision. For the purposes of examination, Examiner will interpret this limitation as “wherein the slave feedback circuit operates based on the clock signal”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stan et al (US 6,538,471).
For claim 1, Stan teaches a flip-flop for a low power integrated circuit (Figure 2), the flip-flop comprising:
a master stage flip-flop (all of 21 and 22 except for G1 and G2);
a slave stage flip-flop (all of 23 and 24 except for G3 and G4); and
a transistor bridge circuit (G1, G2, G3, G4, S1, S2, S3) for sharing a clock signal (
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, which is based on clocks 01 and 02, col. 3, line 22-col 4, line 11) between the master stage flip-flop and the slave stage flip-flop (as understood by examination of Figure 2);
wherein the master stage flip-flop is configured to generate a buffered data output (output of 21) on sensing a low phase of the clock signal (when
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is logic low) from a received data input through a plurality of inverting stages (1st stage: 31 and 32 within 21, 2nd stage: 22; as understood by examination of Figures 2-3) comprising at least one controlled inverter (31, 32) coupled in series with a buffer (22), wherein a master stage internal feedback (path from the output of 21 to the output of 22) within the master stage flip-flop is provided by the buffered data output, the buffered inverted data (output of 22) and a high phase of the clock signal through a pull down network (when
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is logic high G2 forms a pull down network, as understood by examination of Figure 2); and
wherein the slave stage flip-flop is configured to generate a final output (OUT) using the generated buffered data output from the master stage flip-flop (output of 21), wherein the generated buffered data output controls the state of cross-coupled inverters (1st inverter: 31 and 32 within 23, 2nd inverter: 24; as understood by examination of Figures 2-3) connected to the transistor bridge circuit in the slave stage flip-flop (G3, G4), and wherein a slave stage internal feedback within the slave stage flip-flop (output of 24) is provided by the buffered data output and buffered inverted data along with the low phase of the clock signal using the transistor bridge circuit in a pull up network (G1 and G3 provide power to 21 and 23 during the active mode of operation, as understood by examination of Figures 2-3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stan in view of Masleid (US 7,330,054).
For claim 2, Stan teaches the limitations of claim 1 and further teaches that the master stage flip-flop comprises:
a master latch comprising:
a controlled inverting circuit (31, 32); and
a master feedback circuit (22);
wherein the controlled inverting circuit is configured to generate the output of master stage (as understood by examination of Figure 2); and
wherein the master feedback circuit becomes active at a high phase of the clock signal (as understood by examination of Figure 2), and wherein the master feedback circuit is configured to provide the first internal feedback to the flip-flop (as understood by examination of Figure 2).
Stan fails to teach:
an input data-controlled inverter;
wherein the input data-controlled inverter is configured to generate the inverted input data by receiving and inverting the input data in the low phase of the clock signal;
a multistage cascaded controlled inverting circuit;
wherein the multistage cascaded controlled inverting circuit is configured to generate the output of master stage in a form of buffered data output from the received inverted input data;
However, Masleid teaches an optional inverter buffer 110 to “provide transition speed isolation” (col. 3, lines 8-16).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to invert Stan’s input IN using an inverter (such as any one of the inverters within Masleid’s 120) in order to interface between devices (e.g., converting an active low input signal IN to an active high signal or vice versa) and provide transition speed isolation.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art, as evidenced by Masleid.
The combination of Stan and Masleid fails to teach a multistage cascaded controlled inverting circuit as claimed.
However, Masleid also teaches an anti-glitch filter (Figure 1) comprising a multistage cascaded controlled inverting circuit (120, 130), wherein the multistage cascaded controlled inverting circuit is configured to generate an output in a form of buffered data output (as understood by examination of Figure 1).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to incorporate Masleid’s anti-glitch filter into Stan’s invention (wherein 130 is substituted for 31 and 32 within Stan’s 21 such that 130 is connected between G1 and G2) in order to prevent malfunction due to glitches.
Claim(s) 16-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stan in view of Chien et al (US 2023/0253961).
For claim 16, Stan teaches a flip-flop for a low power integrated circuit (Figure 2), the flip-flop comprising:
a master stage flip-flop (all of 21 and 22 except for G1 and G2);
a slave stage flip-flop (all of 23 and 24 except for G3 and G4); and
a transistor bridge circuit (G1, G2, G3, G4, 01, 02) for sharing a clock signal (
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, which is based on clocks 01 and 02, col. 3, line 22-col 4, line 11) between the master stage flip-flop and the slave stage flip-flop (as understood by examination of Figure 2);
wherein the master stage flip-flop is configured to generate a buffered data output (output of 21) on sensing a low phase of the clock signal (when
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is logic low) from a received data input through a plurality of inverting stages (1st stage: 31 and 32 within 21, 2nd stage: 22; as understood by examination of Figures 2-3) comprising at least one controlled inverter (31, 32) coupled in series with a buffer (22), wherein a master stage internal feedback (path from the output of 21 to the output of 22) within the master stage flip-flop is provided by the buffered data output, the buffered inverted data (output of 22) and a high phase of the clock signal through a pull down network (when
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is logic high G2 forms a pull down network, as understood by examination of Figure 2); and
wherein the slave stage flip-flop is configured to generate a final output (OUT) using the generated buffered data output from the master stage flip-flop (output of 21), wherein the generated buffered data output controls the state of cross-coupled inverters (1st inverter: 31 and 32 within 23, 2nd inverter: 24; as understood by examination of Figures 2-3) connected to the transistor bridge circuit in the slave stage flip-flop (G3, G4), and wherein a slave stage internal feedback within the slave stage flip-flop (output of 24) is provided by the buffered data output and buffered inverted data along with the low phase of the clock signal using the transistor bridge circuit i (G1 and G3 provide power to 21 and 23 during the active mode of operation, as understood by examination of Figures 2-3).
Stan fails to teach scan functionality as claimed;
However, Chien teaches a master-slave latch (Figure 1B) comprising a multiplexer (10P) which selectively provides one of the input signals (data input D or scan input SI) to the master latch based on a selection signal (SE, SEN).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add Chien’s multiplexer to select between Stan’s IN and a scan input SI in order to test Stan’s flip flop for abnormalities.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art.
For claim 17, the combination of Stan and Chien as cited above teaches the limitations of claim 16 and further teaches:
the master stage flip-flop receives at least one of:
a data signal (IN, Stan) as an input on the input port based on a state of a scan enable pin of the flip-flop (SE, SEN); and
the scan input signal (SI) as the input based on the state of the scan enable pin of the flip-flop (as understood by Figure 1B of Chen).
For claim 19, the combination of Stan and Chien as cited above teaches the limitations of claim 16 and further teaches:
the slave stage flip-flop comprising:
the cross-coupled inverter coupled to the transistor bridge circuit (via G3, G4);
a slave feedback circuit (24);
wherein the master stage flip-flop controls the output state of the cross-coupled inverter (as understood by the combination of references); and
wherein the slave feedback circuit provides a second internal feedback in the form of previous slave stage output during high phase of the clock signal, through the transistor bridge circuit with common clock transistor when the clock signal is low.
The combination of Stan and Chien fails to teach:
an output inverter;
wherein the cross-coupled inverter is configured to generate the final output through the output inverter using the received scan buffered output from the master stage flip-flop;
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stan in view of Chien and Kim et al (US 2021/0152161).
For claim 20, Stan teaches a flip-flop for a low power integrated circuit (Figure 2), the flip-flop comprising:
a master stage flip-flop (all of 21 and 22 except for G1 and G2);
a slave stage flip-flop (all of 23 and 24 except for G3 and G4); and
a transistor bridge circuit (G1, G2, G3, G4, 01, 02) for sharing a clock signal (
S
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E
P
¯
, which is based on clocks 01 and 02, col. 3, line 22-col 4, line 11) between the master stage flip-flop and the slave stage flip-flop (as understood by examination of Figure 2);
wherein the master stage flip-flop is configured to generate a buffered data output (output of 21) on sensing a low phase of the clock signal (when
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L
E
E
P
¯
is logic low) from a received data input through a plurality of inverting stages (1st stage: 31 and 32 within 21, 2nd stage: 22; as understood by examination of Figures 2-3) comprising at least one controlled inverter (31, 32) coupled in series with a buffer (22), wherein a master stage internal feedback (path from the output of 21 to the output of 22) within the master stage flip-flop is provided by the buffered data output, the buffered inverted data (output of 22) and a high phase of the clock signal through a pull down network (when
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is logic high G2 forms a pull down network, as understood by examination of Figure 2); and
wherein the slave stage flip-flop is configured to generate a final output (OUT) using the generated buffered data output from the master stage flip-flop (output of 21), wherein the generated buffered data output controls the state of cross-coupled inverters (1st inverter: 31 and 32 within 23, 2nd inverter: 24; as understood by examination of Figures 2-3) connected to the transistor bridge circuit in the slave stage flip-flop (G3, G4), and wherein a slave stage internal feedback within the slave stage flip-flop (output of 24) is provided by the buffered data output and buffered inverted data along with the low phase of the clock signal using the transistor bridge circuit i (G1 and G3 provide power to 21 and 23 during the active mode of operation, as understood by examination of Figures 2-3).
Stan fails to teach:
scan functionality as claimed; and
the flip-flop is a reset flip-flop having an asynchronous reset input signal.
However, Chien teaches a master-slave latch (Figure 1B) comprising a multiplexer (10P) which selectively provides one of the input signals (data input D or scan input SI) to the master latch based on a selection signal (SE, SEN).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add Chien’s multiplexer to select between Stan’s IN and a scan input SI in order to test Stan’s flip flop for abnormalities.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art.
The combination of Stan and Chien as cited above fails to teach the reset functionality as claimed.
However, Kim teaches in Figure 5 resetting (via RST) a inverter (140) such that during a reset state, a positive power supply is disconnected from the clocked inverter (via 120) and the output of the clocked inverter is connected to ground (via 160).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add Kim’s reset transistors (120, 160) to Stan’s 21 and 23 (such that a first instance of 120 and a second instance of 120 are directly connected between Vdd and G1 and G3, respectively, and a first instance of 160 and a second instance of 160 is directly connected between ground and the outputs of 21 and 23, respectively) in order to fix unstable or error conditions by returning the circuit to a known, stable state.
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art, as evidenced by Kim.
Allowable Subject Matter
Claims 3-15 and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Specifically, the prior art fails to teach the details of the transistor bridge circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jain (US 2008/0218234) teaches a low power flip flop circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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