DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to the Preliminary Amendment dated 7/29/2025.
Claim 1 is amended.
Claims 2-21 are added.
Claims 1-21 are pending.
Claims 1-21 are rejected.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on 11/7/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSes) submitted on 5/14/2025 and 7/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…a controller configured to generate a table including a mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table, to determine empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table and to translate a physical address mapped to a logical address corresponding to the target namespace, wherein, when the empty memory regions corresponding to the target namespace are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions corresponding to the target namespace are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other” (independent claim 1, lines 7-19).
The Examiner is uncertain if the recitation of “…a table including a mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table..” means any of the following possible interpretations:
“a table including a mapping information between the plurality of memory regions and one or more namespaces” is used “to record information on empty memory regions” such that “empty memory regions, among the plurality of memory regions, that are not mapped to any namespace” that is included “in the table” are used to store data or other information;
“a table including a mapping information between the plurality of memory regions and one or more namespaces” is used “to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table” such that “a table” records “information” regarding “empty memory regions, that are not mapped to any namespace” that is included “in the table”;
“information” about “empty memory regions, among the plurality of memory regions, that are not mapped to any namespace” that is included in “a table” that includes “a mapping information between the plurality of memory regions and one or more namespaces” is stored “in the table”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…a controller configured to generate a table including a mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table, to determine empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table and to translate a physical address mapped to a logical address corresponding to the target namespace, wherein, when the empty memory regions corresponding to the target namespace are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions corresponding to the target namespace are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other” to read “…a controller configured to generate a table that includes a mapping information between the plurality of memory regions and one or more namespaces, to record, in the table, information about empty memory regions, among the plurality of memory regions, that are not mapped to any namespace, to determine empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table, and to translate a physical address mapped to a logical address corresponding to the target namespace, wherein, when the empty memory regions corresponding to the target namespace are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions corresponding to the target namespace are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other.”
Dependent claims 2-8, which ultimately depend from independent claim 1, are rejected for carrying the same deficiencies.
Claims 9-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 9 recites “…a controller configured to perform an address translation by an address mapper including mapping information between the plurality of memory blocks and one or more namespaces, to record information on empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace in the address mapper, to determine empty memory blocks to be mapped to a target namespace from among the empty memory blocks recorded in the address mapper, wherein, when the empty memory blocks corresponding to the target namespace are sequential, a physical address range of the empty memory blocks mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory blocks corresponding to the target namespace are non-sequential, the physical address range of the empty memory blocks mapped to the target namespace are two or more physical address ranges non-consecutive to each” (independent claim 9, lines 3-13).
The Examiner is uncertain if the recitation of “…an address mapper including mapping information between the plurality of memory blocks and one or more namespaces, to record information on empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace in the address mapper…” means any of the following possible interpretations:
“an address mapper including mapping information between the plurality of memory blocks and one or more namespaces” is used “to record information on empty memory blocks” such that “empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace” that is included “in the address mapper” are used to store data or other information;
“an address mapper including mapping information between the plurality of memory blocks and one or more namespaces” is used “to record information on empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace in the address mapper” such that “an address mapper” records “information” regarding “empty memory blocks, that are not mapped to any namespace” that is included “in the address mapper”;
“information” about “empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace” that is included in “an address mapper” that includes “mapping information between the plurality of memory blocks and one or more namespaces” is stored “in the address mapper”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…a controller configured to perform an address translation by an address mapper including mapping information between the plurality of memory blocks and one or more namespaces, to record information on empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace in the address mapper, to determine empty memory blocks to be mapped to a target namespace from among the empty memory blocks recorded in the address mapper, wherein, when the empty memory blocks corresponding to the target namespace are sequential, a physical address range of the empty memory blocks mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory blocks corresponding to the target namespace are non-sequential, the physical address range of the empty memory blocks mapped to the target namespace are two or more physical address ranges non-consecutive to each” to read “…a controller configured to perform an address translation by an address mapper that includes mapping information between the plurality of memory blocks and one or more namespaces, to record, in the address mapper, information about empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace in the address mapper, to determine empty memory blocks to be mapped to a target namespace from among the empty memory blocks recorded in the address mapper, wherein, when the empty memory blocks corresponding to the target namespace are sequential, a physical address range of the empty memory blocks mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory blocks corresponding to the target namespace are non-sequential, the physical address range of the empty memory blocks mapped to the target namespace are two or more physical address ranges non-consecutive to each.”
Dependent claims 10-14, which ultimately depend from independent claim 9, are rejected for carrying the same deficiencies.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 15 recites “…generating a table including a mapping information between a plurality of memory regions and one or more namespaces; recording information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table; determining empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table; and translating a physical address mapped to a logical address corresponding to the target namespace on the basis of an offset of the logical address, when the empty memory regions to be mapped to the target namespace are sequential; and translating the physical address mapped to the logical address corresponding to the target namespace on the based of the table including the mapping information, when the empty memory regions to be mapped to the target namespace are non-sequential” (independent claim 15, lines 2-15).
The Examiner is uncertain if the recitation of “…generating a table including a mapping information between a plurality of memory regions and one or more namespaces; recording information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table…” means any of the following possible interpretations:
“a table including a mapping information between a plurality of memory regions and one or more namespaces” is used for “recording information on empty memory regions” such that “empty memory regions, among the plurality of memory regions, that are not mapped to any namespace” that is included “in the table” are used to store data or other information;
“a table including a mapping information between a plurality of memory regions and one or more namespaces” is used “to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table” such that “a table” records “information” regarding “empty memory regions, that are not mapped to any namespace” that is included “in the table”;
“information” about “empty memory regions, among the plurality of memory regions, that are not mapped to any namespace” that is included in “a table” that includes “a mapping information between a plurality of memory regions and one or more namespaces” is stored “in the table”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…generating a table including a mapping information between a plurality of memory regions and one or more namespaces; recording information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table; determining empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table; and translating a physical address mapped to a logical address corresponding to the target namespace on the basis of an offset of the logical address, when the empty memory regions to be mapped to the target namespace are sequential; and translating the physical address mapped to the logical address corresponding to the target namespace on the based of the table including the mapping information, when the empty memory regions to be mapped to the target namespace are non-sequential” to read “…generating a table including a mapping information between a plurality of memory regions and one or more namespaces; recording, in the table, information about empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table; determining empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table; and translating a physical address mapped to a logical address corresponding to the target namespace on the basis of an offset of the logical address, when the empty memory regions to be mapped to the target namespace are sequential; and translating the physical address mapped to the logical address corresponding to the target namespace on the based of the table including the mapping information, when the empty memory regions to be mapped to the target namespace are non-sequential.”
Claims 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 16 recites “…a memory controller configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive, set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, and translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions” (independent claim 16, lines 3-16).
The Examiner is uncertain if the recitation of “…generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table…” means any of the following possible interpretations:
“mapping information between a plurality of namespaces and a plurality of logical block addresses” is recorded as “information on one or more logical block addresses that are not mapped to any namespace in a table” as part of a step of generating mapping information;
“mapping information between a plurality of namespaces and a plurality of logical block addresses” is recorded “in a table” as “information on one or more logical block addresses that are not mapped to any namespace” as part of a step of generating mapping information; or
Some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…a memory controller configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive, set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, and translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions” to read “…a memory controller configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record, in a table, information about one or more logical block addresses that are not mapped to any namespace; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive, set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, and translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions.”
Dependent claims 17-18, which ultimately depend from independent claim 16, are rejected for carrying the same deficiencies.
Claims 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 19 recites “…wherein the host interface layer is configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive; and set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, wherein the flash translation layer is configured to translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions” (independent claim 19, lines 6-19).
The Examiner is uncertain if the recitation of “…generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table…” means any of the following possible interpretations:
“mapping information between a plurality of namespaces and a plurality of logical block addresses” is recorded as “information on one or more logical block addresses that are not mapped to any namespace in a table” as part of a step of generating mapping information;
“mapping information between a plurality of namespaces and a plurality of logical block addresses” is recorded “in a table” as “information on one or more logical block addresses that are not mapped to any namespace” as part of a step of generating mapping information; or
Some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…wherein the host interface layer is configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive; and set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, wherein the flash translation layer is configured to translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions” to read “…wherein the host interface layer is configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record, in a table, information about one or more logical block addresses that are not mapped to any namespace; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive; and set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, wherein the flash translation layer is configured to translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions”
Dependent claims 20-21, which ultimately depend from independent claim 19, are rejected for carrying the same deficiencies.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim 1 of the instant application is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,321,261 (“Kwon”) in view of USPGPUB 2019/0347010 (“Frolikov”).
Claims 9 and 15-16 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 8 of U.S. Patent No. 12,321,261 (“Kwon”).
The following tables, in which similarities between claims 1, 9, and 15-16 of the instant application and claims 1 and 8 of Kown are highlighted in bold, and accompanying reasoning illustrate that claim 1 of the instant application is not patentably distinct from claim 1 of Kwon in view of Frolikov and that claims 9 and 15-16 of the instant application are not patentably distinct from claims 1 and 8 of Kwon:
Instant Application, Independent Claim 1
Kwon, Independent Claim 1
A computing system comprising: a host device configured to provide a namespace command comprising a target namespace having a target size to a storage device; and the storage device configured to receive the namespace command, wherein the storage device comprises: a memory including a plurality of memory regions; and a controller configured to generate a table including a mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table, to determine empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table and to translate a physical address mapped to a logical address corresponding to the target namespace, wherein, when the empty memory regions corresponding to the target namespace are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions corresponding to the target namespace are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other.
1. A storage device comprising: a memory including a plurality of memory regions; and a controller configured to generate mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace, in a table including the information on empty memory regions, and to determine, when a target namespace, which is a logical partition mapped to at least one of the plurality of memory regions, having a target size is created, empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table including the information on empty memory regions, wherein the controller sets a flag corresponding to the target namespace as a first flag when empty memory regions mapped to the target namespace are sequential, sets a flag corresponding to the target namespace as a second flag when empty memory regions corresponding to the target namespace are non-sequential, and translates a physical address mapped to a logical address corresponding to the target namespace according to a flag corresponding to the target namespace, wherein, when the empty memory regions are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other.
Kwon does not appear to explicitly claim “A computing system comprising: a host device configured to provide a namespace command comprising a target namespace having a target size to a storage device; and the storage device configured to receive the namespace command, wherein the storage device comprises“; however, in an analogous art, Frolikov teaches namespaces allocation in non-volatile memory devices.
As per claim 1, Frolikov particularly teaches:
a computing system comprising: a host device configured to provide a namespace command comprising a target namespace having a target size to a storage device; and the storage device configured to receive the namespace command, wherein the storage device comprises: (Frolikov, Abstract; FIG. 1, reference numerals 101 and 103; FIG. 12; and paragraphs 0028-0042 and 0120-0144, where the system of Frolikov includes an external host system that transmits namespace creation and allocation commands to a non-volatile memory device in order to allocate empty memory blocks within the non-volatile memory device for use by namespaces created by the external host system. Frolikov therefore particularly teaches a computing system comprising: a host device configured to provide a namespace command comprising a target namespace having a target size to a storage device; and the storage device configured to receive the namespace command, wherein the storage device comprises).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Frolikov and the claims of Kwon before them before the instant application was effectively filed, to modify the claims of Kwon to include the principles of Frolikov of enabling namespace allocation and management by a non-volatile memory device.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance by implementing techniques that increase processing speed and memory transfer rates by integrating processing and memory of a memory device (Frolikov, paragraph 0039).
Instant Application, Independent Claim 9
Kwon, Independent Claim 1,
9. A storage device comprising: a memory including a plurality of memory blocks; and a controller configured to perform an address translation by an address mapper including mapping information between the plurality of memory blocks and one or more namespaces, to record information on empty memory blocks, among the plurality of memory blocks, that are not mapped to any namespace in the address mapper, to determine empty memory blocks to be mapped to a target namespace from among the empty memory blocks recorded in the address mapper, wherein, when the empty memory blocks corresponding to the target namespace are sequential, a physical address range of the empty memory blocks mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory blocks corresponding to the target namespace are non-sequential, the physical address range of the empty memory blocks mapped to the target namespace are two or more physical address ranges non-consecutive to each.
1. A storage device comprising: a memory including a plurality of memory regions; and a controller configured to generate mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace, in a table including the information on empty memory regions, and to determine, when a target namespace, which is a logical partition mapped to at least one of the plurality of memory regions, having a target size is created, empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table including the information on empty memory regions, wherein the controller sets a flag corresponding to the target namespace as a first flag when empty memory regions mapped to the target namespace are sequential, sets a flag corresponding to the target namespace as a second flag when empty memory regions corresponding to the target namespace are non-sequential, and translates a physical address mapped to a logical address corresponding to the target namespace according to a flag corresponding to the target namespace, wherein, when the empty memory regions are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other.
Instant Application, Independent Claim 15
Kwon, Independent Claim 8
15. A method for operating a storage device, comprising: receiving, from an external device, a command including a target namespace having a target size; generating a table including a mapping information between a plurality of memory regions and one or more namespaces; recording information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace in the table; determining empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table; and translating a physical address mapped to a logical address corresponding to the target namespace on the basis of an offset of the logical address, when the empty memory regions to be mapped to the target namespace are sequential; and translating the physical address mapped to the logical address corresponding to the target namespace on the basis of the table including the mapping information, when the empty memory regions to be mapped to the target namespace are non-sequential.
8. A method for operating a storage device, comprising: receiving, from an external device, a command indicating that a target namespace, which is a logical partition mapped to at least one of a plurality of memory regions, having a target size has been created; searching for empty memory regions to be mapped to the target namespace, in a table including information on empty memory regions, in which the information on empty memory regions not mapped to any namespace among the plurality of memory regions is recorded; mapping the searched empty memory regions to the target namespace; setting, according to whether the empty memory regions mapped to the target namespace are sequential or non-sequential, a flag corresponding to the target namespace as a first flag or a second flag; and determining a physical address mapped to a logical address corresponding to the target namespace according to a flag corresponding to the target namespace, wherein, when the empty memory regions mapped to the target namespace are sequential, a physical address range of the empty memory regions is one consecutive physical address range, and wherein, when the empty memory regions mapped to the target namespace are non-sequential, the physical address range of the empty memory regions are two or more physical address ranges non-consecutive to each other.
Instant Application, Independent Claim 16
Kwon, Independent Claim 1
16. A storage device comprising: a memory device including a plurality of memory regions; and a memory controller configured to: generate mapping information between a plurality of namespaces and a plurality of logical block addresses, to record information on one or more logical block addresses that are not mapped to any namespace in a table; determine, when a target namespace, which is a logical partition mapped to at least one logical block address, having a target size is created, logical block addresses to be mapped to the target namespace based on the mapping information in the table, set a flag corresponding to the target namespace as a first flag when the logical block addresses mapped to the target namespace are consecutive, set a flag corresponding to the target namespace as a second flag when the logical block addresses mapped to the target namespace are non-consecutive, and translate, according to the flag corresponding to the target namespace, the logical block addresses mapped to the target namespace to one or more physical block addresses corresponding to the plurality of memory regions.
1. A storage device comprising: a memory including a plurality of memory regions; and a controller configured to generate mapping information between the plurality of memory regions and one or more namespaces, to record information on empty memory regions, among the plurality of memory regions, that are not mapped to any namespace, in a table including the information on empty memory regions, and to determine, when a target namespace, which is a logical partition mapped to at least one of the plurality of memory regions, having a target size is created, empty memory regions to be mapped to the target namespace from among the empty memory regions recorded in the table including the information on empty memory regions, wherein the controller sets a flag corresponding to the target namespace as a first flag when empty memory regions mapped to the target namespace are sequential, sets a flag corresponding to the target namespace as a second flag when empty memory regions corresponding to the target namespace are non-sequential, and translates a physical address mapped to a logical address corresponding to the target namespace according to a flag corresponding to the target namespace, wherein, when the empty memory regions are sequential, a physical address range of the empty memory regions mapped to the target namespace is one consecutive physical address range, and wherein, when the empty memory regions are non-sequential, the physical address range of the empty memory regions mapped to the target namespace are two or more physical address ranges non-consecutive to each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
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