CTNF 19/208,141 CTNF 82201 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT Information Disclosure Statement As required by M.P.E.P. ' 609 (C) , the applicant's submission of the Information Disclosure Statement, dated 5/14/25, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2) , a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action. 07-30-03-h AIA 2. CLAIM INTERPRETATION Claim Interpretation – USC 112 f/6th 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. 07-30-06 This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “decoder logic …to translate an HPA included in the memory access request to a DPA for the pooled memory device based on the information maintained in the plurality of decoder registers” as recited in claims 1-12. The Examiner notes paragraphs 51-66 of the Applicant’s specification discusses the structure of the “decoder logic” and its corresponding algorithm. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. 3. REJECTIONS BASED ON PRIOR ART 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC ' 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1-18 is /ar e rejected under 35 U.S.C. 103 as being unpatentable over Taval laei (US 11210218) in view of Ayoub (US 9804988). With r espect to claim 1, the Tavallaei reference teaches an apparatus comprising: a decoder capable of being dynamically programmable by one or more host nodes of a disaggregated memory architecture (DMA), wherein the decoder is dynamically programmable to maintain information to translate host physical addresses (HPAs) included in memory access requests to device physical addresses (DPAs) for a pooled memory device accessible by the one or more host nodes, (column 8, lines 26-39, where for each DPA, identifying a target address decoder (TAD) for an allocation slice of the disaggregated memory pool that the DPA corresponds to. As will be described in more detail below, a TAD generally refers to a function used to map memory addresses of a particular allocation slice to media-specific physical elements of one or more physical memory units—e.g., discrete RAM DIMMs; and column 5, lines 39-51, where method 200 includes receiving an indication of one or more ranges of HPAs from a compute node of a plurality of compute nodes communicatively coupled to a disaggregated memory pool) and wherein the HPAs are translated to DPAs based on the DPAs mapping to one or more memory address regions of the pooled memory device, each of the one or more memory address regions to have a predetermined memory size granularity; (column 6, lines 12-25, where each allocation slice may be 1 GB in size, although other suitable sizes may be used—e.g., 512 MB, 2 GB, 4 GB. The disaggregated memory pool may additionally have any suitable total capacity. For example, the disaggregated memory pool may have 1 TB of total memory, divided between 1024 1 GB allocation slices, although any other suitable values may be used) and decoder logic, responsive to a memory access request to the pooled memory device, to translate an HPA included in the memory access request to a DPA for the pooled memory device based on the information maintained in the decoder. (column 13, lines 25-60, where there is a conversion of the two or more ranges of HPAs into a contiguous range of device physical addresses (DPAs); and for each DPA, identify a target address decoder (TAD) for an allocation slice of the disaggregated memory pool that the DPA corresponds to, based on a slice identifier included in the DPA and a slice-to-TAD index) However, the Tavallaei reference does not explicitly teach the decoder are a plurality of decoder registers. The Ayoub reference teaches it is conventional to have the decoder be a plurality of decoder registers. (column 13, lines 7-14, where to access memory block 750 on the device , the host uses reserved memory block 730 and a BAR for memory block 730 to set control registers 760 on the device, such that address 0xYY in the host memory space can be translated into address 0xZZ in the device memory space. In this way, the host may read/write memory block 720 as if it were actually reading or writing memory block 750 in device memory 740 as described above) It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Tavallaei reference to have the decoder be a plurality of decoder registers, as taught by the Ayoub reference. The suggestion/motivation for doing so would have been to allow dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit. (Ayoub, abstract) Therefore it would have been obvious to combine the Tavallaei and Ayoub references for the benefits shown above to obtain the invention as specified in the claim. With respect to claim 2, the combination of the Tavallaei and Ayoub references teaches the apparatus of claim 1, wherein the plurality of decoder registers are capable of being dynamically programmable during run time of the pooled memory device. (Ayoub, column 8, lines 54-64, where while scanning the buses, or possibly after, processors 102 may also transmit configuration transactions to each of the devices it discovers. The configuration may include, for example, assigning the memory address space and the I/O address space. The configuration may further include programming information, such as a bus number and/or a device number, into configuration registers in the devices. During the configuration, processors 102 may also read information from configuration registers in the device. In most implementations, the configuration registers are included in the hardware of a device) With respect to claim 3, the combination of the Tavallaei and Ayoub references teaches the apparatus of claim 1, wherein the DPA is to be provided to a memory controller for the pooled memory device to enable memory access to a memory address region included in the one or more memory address regions. (Tavallaei, column 8, lines 26-39, where for each DPA, identifying a target address decoder (TAD) for an allocation slice of the disaggregated memory pool that the DPA corresponds to. As will be described in more detail below, a TAD generally refers to a function used to map memory addresses of a particular allocation slice to media-specific physical elements of one or more physical memory units—e.g., discrete RAM DIMMs; and column 5, lines 39-51, where method 200 includes receiving an indication of one or more ranges of HPAs from a compute node of a plurality of compute nodes communicatively coupled to a disaggregated memory pool) With respect to claim 4, the combination of the Tavallaei and Ayoub references teaches the apparatus of claim 1, wherein at least one of the plurality of decoder registers is dynamically programmable to enable the one or more host nodes to dynamically allocate or de-allocate at least one of the one or more memory address regions of the pooled memory device. (Ayoub, column 8, lines 37-53, where the absolute memory address range in the system memory allocated to a PCIe device may be based on which slot the PCIe device is plugged into. A PCIe device may be assigned a default size, such as 16 MBs of memory space. If a PCIe device requests more memory space, the memory assignment may be adjusted accordingly) With respect to claim 5, the combination of the Tavallaei and Ayoub references teaches the apparatus of claim 1, wherein the one or more memory address regions comprise multiple memory address regions that are non-contiguous memory address regions of the pooled memory device. (Tavallaei, column 6, lines 26-37, where the set of HPAs received by a memory control system from a particular compute node may be non-contiguous—e.g., there may be a gap in available HPAs between where one allocation slice ends and another begins) With respect to claim 6, the combination of the Tavallaei and Ayoub references teaches 6. The apparatus of claim 1, wherein the predetermined memory size granularity comprises multiples of 256MB. (Tavallaei, column 6, lines 12-25, where each allocation slice may be 1 GB in size, although other suitable sizes may be used—e.g., 512 MB, 2 GB, 4 GB. The disaggregated memory pool may additionally have any suitable total capacity) Claims 7-12 are the system implementation of claims 1-6, and rejected under a similar rationale as shown above. The Examiner notes the Tavallaei reference (see fig. 1-2 and corresponding text) teaches “a pooled memory device accessible by one or more host nodes of a disaggregated memory architecture (DMA); and a memory pooling circuitry configured to” perform the steps/algorithm noted above. Claims 13-18 are the non-transitory machine readable storage medium implementation of claims 1-6, and rejected under a similar rationale as shown above. 4. RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c) . 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include: Qawami (US 20190205030), which teaches techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device. 5. CLOSING COMMENTS Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PRASITH THAMMAVONG/ Primary Examiner, Art Unit 2137 Application/Control Number: 19/208,141 Page 2 Art Unit: 2137 Application/Control Number: 19/208,141 Page 3 Art Unit: 2137 Application/Control Number: 19/208,141 Page 4 Art Unit: 2137 Application/Control Number: 19/208,141 Page 5 Art Unit: 2137 Application/Control Number: 19/208,141 Page 6 Art Unit: 2137 Application/Control Number: 19/208,141 Page 7 Art Unit: 2137 Application/Control Number: 19/208,141 Page 8 Art Unit: 2137 Application/Control Number: 19/208,141 Page 9 Art Unit: 2137 Application/Control Number: 19/208,141 Page 10 Art Unit: 2137 Application/Control Number: 19/208,141 Page 11 Art Unit: 2137 Application/Control Number: 19/208,141 Page 12 Art Unit: 2137
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