Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/13/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brennan et al PG Pub US 2019/0073265 A1 [hereinafter Brennan].
Regarding claims 1, 8, & 15, Brennan discloses:
a storage class solid state memory (The persistent storage resource 170A-B main include any number of storage drives 171A-F (also referred to as “storage devices” herein) [0032]);
a non-storage class solid state memory (The persistent storage resource 170A-B main include… any number of non-volatile Random Access Memory (‘NVRAM’) devices (not shown) [0032]); and
a processing device external to the storage class solid state memory and the non-storage class solid state memory (Storage array controller 110), the processing device configured to: store a first data shard of a redundant array of inexpensive drives (RAID) stripe in the storage class solid state memory (FIG. 13 also includes receiving (1002) a first portion of data 1052 of a RAID stripe for writing to a first memory location of a first plurality of solid state drives [0172]);
generate parity data for the RAID stripe (FIG. 13 sets forth a flow chart illustrating an example method for incremental RAID stripe update parity calculation according to some embodiments of the present disclosure [0172]);
store the parity data for the RAID stripe in the non-storage class solid state memory (the saving of the first parity value is shown in Fig. 10 as first parity value (1054) [0163];
store a second data shard of the RAID stripe in the storage class solid state memory (receiving (1006) a second portion of data 1056 of the RAID stripe for writing to a second memory location that is different from the first memory location [0172]);
generate updated parity data for the RAID stripe (calculating a second parity value 1058 in dependence upon the second portion of data 1056 of the RAID stripe and upon the first parity value 1054 [0172]); and
store the updated parity data for the RAID stripe in the non-storage class solid state memory (responsive to successfully writing the second portion of data 1056 of the RAID stripe, replacing (1010) the first parity value 1054 with the second parity value 1058 [0172]).
Regarding claims 2, 9, & 16, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15. Brennan also discloses:
wherein the non-storage class solid state memory comprises non-volatile random access memory (NVRAM) (the NVRAM devices of a persistent storage resource 170A-B may be configured to receive, from the storage array controller 110, data to be stored in the storage drives 171A-F [0033]).
Regarding claims 3, 10, & 17, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15. Brennan also discloses:
wherein the first data shard and the second data shard are stored in the storage class solid state memory while bypassing storing the first data shard and the second data shard in the non-storage class solid state memory (In some examples, writing data to the NVRAM device may be carried out more quickly than directly writing data to the storage drive 171A-F. In implementations, the storage array controller 110 may be configured to utilize the NVRAM devices as a quickly accessible buffer for data destined to be written to the storage drives 171A-F. [0033] since “some examples” is not the totality of all instances, there are instances where the are stored in the flash without being stored in the NVRAM).
Regarding claims 4, 11, & 18, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15. Brennan also discloses:
wherein the first data shard and the second data shard are stored in the storage class solid state memory using a quad-level cell (QLC) programming mode, while avoiding storing the first data shard and the second data shard using a single-level cell (SLC) programming mode (the storage resources 308 may include flash memory, including single-level cell (‘SLC’) NAND flash, multi-level cell (‘MLC’) NAND flash, triple-level cell (‘TLC’) NAND flash, quad-level cell (‘QLC’) NAND flash [0016]) in the case where all of the flash memory is QLC, the second data would inherently avoid SLC).
Regarding claims 5, 12, & 19, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15. Brennan also discloses:
wherein the processing device is further configured to:determine whether all data shards for the RAID stripe have been stored in the storage class memory; in response to determining that all the data shards for the RAID stripe have been stored, generate final parity data for the RAID stripe; and store the final parity data in the storage class solid state memory (responsive to successfully writing the second portion of data 1056 of the RAID stripe, replacing (1010) the first parity value 1054 with the second parity value 1058 [0172]).
Regarding claims 6, 13, & 20, the limitations of these claims have been noted in the rejection of claims 1, 8, & 15. Brennan also discloses:
wherein the storage class solid state memory comprises flash memory (the storage drive 171A-F may be one or more solid-state drives (‘SSDs’), flash memory based storage [0034]).
Regarding claims 7 & 14, the limitations of these claims have been noted in the rejection of claims 1 & 8. Brennan also discloses:
wherein the storage system comprises a plurality of managed flash storage devices comprising the storage class solid state memory and the non- storage class solid state memory (The persistent storage resource 170A-B main include any number of storage drives 171A-F (also referred to as “storage devices” herein) and any number of non-volatile Random Access Memory (‘NVRAM’) devices (not shown) [0032]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN D ROSSITER whose telephone number is (571)270-3788. The examiner can normally be reached M-F 8AM-4PM.
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/SEAN D ROSSITER/Primary Examiner, Art Unit 2133
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