DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Govindarajan et al. (Pub. No. US20230333858)
As per claim 1, Govindarajan discloses an apparatus configured for machine learning acceleration (fig.1, apparatus 100), the apparatus comprising:
a system direct memory access (DMA) engine (fig.1, DMA 120) communicatively coupled to a system memory (fig.1, memory 102); and
at least one core (fig.1, core 112) communicatively coupled to the system DMA engine (fig.1, DMA 120) via an interconnect(fig.1, interconnect 110), wherein the system DMA engine is configured to transfer data to local memory (fig.1, internal memory 106) in the at least one core via the interconnect, each core comprising a one or more slices wherein each slice (paragraph 33, lines 1-2, DMA circuitry 132 may transfer slices of a boot image from the memory device 102 as a result of requesting access to a specific slice) comprises a compute engine(fig. 1, BBDAc 104), each compute engine comprises:
input data memory communicatively coupled to receive the data from the local memory (fig.1, internal memory 106);
one or more sub-compute engines, each sub-compute engine is separately communicatively coupled to the input data memory (paragraph 95, 12-13, the sub-slice boundary corresponds to a boundary of a block comprising the memory device 102) and is configured to perform a compute operation on the data stored in the input data memory (paragraph 73, lines 11-13, he slice operations 530-540 enable the operations represented by a slice to be performed by a compute core while loading another slice of the boot image); and
partial data memory communicatively coupled to receive and store a compute output from each of the one or more sub-compute engines (paragraph 27, BBDAc 104 is configured to load, authenticate, and/or decompress one or more portions of one or more boot images stored in the memory device 102 based on either an access request generated by the compute cores 112 and/or 114).
As per claim 2, Govindarajan discloses wherein each slice is coupled to receive the data from the local memory and is not directly connected to another slice (paragraph 104, access a slice of a boot image directly from the internal memory 106 as a result of determining that the image has been completely transferred to internal memory 106).
As per claim 3, Govindarajan discloses wherein each core further comprises a compute sub-system coupled to the local memory and that operates in parallel with the one or more slices (paragraph 129, elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor).
As per claim 4, Govindarajan discloses wherein the compute sub-system performs subroutines that are not performed in the one or more slices (paragraph 23, the BBDAc may determine a slice of the image stored in one or more blocks of the block device to load and authenticate based on the request from the compute core.)
As per claim 5, Govindarajan discloses wherein each slice further comprises a descriptor execution engine configured to execute descriptors and to receive the compute output from the partial data memory (paragraph 84, generating a signature table and/or preload headers may alternatively be used in accordance with the in accordance with this description).
As per claim 6, Govindarajan discloses wherein the descriptor execution engine is further configured to run at least one of activation functions and scaling functions on the compute output from the compute engine, and to operate on shaping the compute output and to send the compute output to the local memory (paragraph 84, generating a signature table and/or preload headers may alternatively be used in accordance with the in accordance with this description).
As per claim 7, Govindarajan discloses wherein the input data memory in each compute engine receives and stores the data via an input data bus (fig.11, a bus 1118) for transferring input data and a weights bus for transferring weights, and wherein the partial data memory transfers the compute output via an output data bus (paragraph 30, The access scheduler circuitry 130 is configured to control access to the memory device 102 and establishes based on either a high or low priority of the transaction via bus).
As per claim 8, Govindarajan discloses wherein the input data is transferred via the weights bus and the weights are transferred via the input data bus when an input data frame size is less than a predetermined number of bytes (paragraph 53, lines 4-5, The memory device 102 is a block storage device whose data may only be accessed in portions of a predetermined data size).
As per claim 9, Govindarajan discloses wherein compute outputs from each of the one or more sub-compute engines are accumulated in the partial data memory (paragraph 50, the address remapping circuitry 122 may request a portion of the boot image to be transferred with a high priority by transferring the portion of the image using the foreground DMA circuitry).
As per claim 10, Govindarajan discloses a method for performing machine learning acceleration, the method comprising:
transferring data with a system direct memory access (DMA) engine (fig.1, DMA 120) from a system memory (fig.1, memory 102) to local memory in at least one core (fig.1, core 112) via an interconnect (fig.1, interconnect 110), wherein each core comprises one or more slices, each slice comprising a compute engine (paragraph 33, lines 1-2, DMA circuitry 132 may transfer slices of a boot image from the memory device 102 as a result of requesting access to a specific slice);
transferring the data from the local memory (fig.1, internal memory 106) to an input memory in the compute engine of each slice (paragraph 97, lines 3-4, the BBDAc 104 may transfer the remaining slices of the image based on a sequential order of the slices in the memory device 102);
transferring the data from the input memory to one or more sub-compute engines, wherein each sub-compute engine is independent of other sub-compute engines (paragraph 95, 12-13, the sub-slice boundary corresponds to a boundary of a block comprising the memory device 102);
performing independent compute operations on the data by each sub-compute engine (paragraph 73, lines 11-13, he slice operations 530-540 enable the operations represented by a slice to be performed by a compute core while loading another slice of the boot image); and
receiving and storing in partial data memory in the compute engine a compute output from each of the one or more sub-compute engines (paragraph 27, BBDAc 104 is configured to load, authenticate, and/or decompress one or more portions of one or more boot images stored in the memory device 102 based on either an access request generated by the compute cores 112 and/or 114).
As per claim 11, Govindarajan discloses wherein the data is transferred from the local memory to the input memory with an input data bus for transferring input data and a weights bus for transferring weights(paragraph 30, The access scheduler circuitry 130 is configured to control access to the memory device 102 and establishes based on either a high or low priority of the transaction).
As per claim 12, Govindarajan discloses wherein the input data is transferred via the weights bus and the weights are transferred via the input data bus when an input data frame size is less than a predetermined number of bytes (paragraph 53, lines 4-5, The memory device 102 is a block storage device whose data may only be accessed in portions of a predetermined data size).
As per claim 13, Govindarajan discloses the method further comprising transferring the compute output from the partial data memory to the local memory with an output data bus(paragraph 30, The access scheduler circuitry 130 is configured to control access to the memory device 102 and establishes based on either a high or low priority of the transaction).
As per claim 14, Govindarajan discloses wherein each slice further comprises a descriptor execution engine and the compute output is transferred from the partial data memory to the local memory via the descriptor execution engine, the method further comprising performing at least one of activation and scaling functions with the descriptor execution engine to shape the compute output(paragraph 84, generating a signature table and/or preload headers may alternatively be used in accordance with the in accordance with this description).
As per claim 15, Govindarajan discloses the method further comprising accumulating compute outputs from each of the one or more sub-compute engines in the partial data memory (paragraph 84, generating a signature table and/or preload headers may alternatively be used in accordance with the in accordance with this description).
As per claim 16, Govindarajan discloses wherein output data from each compute engine is transferred to the system memory via the local memory and the system DMA engine (paragraph 32, lines 2-5, DMA circuitry 132 transfers slices to the boot image from the memory device 102 based on an order specified by either a preload header corresponding to the boot image or linear memory addresses of the slices).
As per claim 17, Govindarajan discloses wherein transferring the data from the local memory to the input memory in the compute engine of each slice comprises transferring the data to a plurality of slices within each core, wherein each slice in the plurality of slices is independent of all other slices in the plurality of slices(paragraph 30, The access scheduler circuitry 130 is configured to control access to the memory device 102 and establishes based on either a high or low priority of the transaction)..
As per claim 18, Govindarajan discloses wherein each core further comprises a compute sub-system, the method further comprising: transferring the data from the local memory to the compute sub-system (paragraph 95, lines 15-16, the sub-slice boundary corresponds to a boundary of a block comprising the memory device 102); and performing subroutines with the compute sub-system that are not performed in the one or more slices (paragraph 95, lines 11-14, the access scheduler circuitry 130 may halt the preloading operation of a multi-block slice being performed by the background DMA circuitry 132 on a block boundary as a result of receiving a high priority access request).
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Govindarajan et al. (Pub. No. US20230333858) in view of Parikh et al. (Pub. No. US 20210157648)
As per claim 19, Govindarajan discloses all the limitations as the above but does not explicitly disclose wherein the compute sub-system in each core comprises a RISC-V microprocessor. However, Parikh discloses this (paragraph 111, processor 360 may be a nano-processor, reduced instruction set computer (RISC) (e.g., RISC-V), microprocessor, or any other structure that may perform processing.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Parikh with the teaching of Govindarajan so as the architecture keeps instruction execution simple. This simplicity makes chip design faster, reduces hardware complexity, and improves energy efficiency, thus enhance the system performance.
As per claim 20. Parikh discloses wherein the local memory is double buffered (paragraph 84, line 17, buffer tracking may be synonymous to double buffering).
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Gibson et al. [Pub. No. US20170323196] discloses a method in a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: receiving a first subset of data comprising at least a portion of weight data and at least a portion of input data for a CNN layer and performing, using at least one convolution engine, a convolution of the first subset of data to generate a first partial result.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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