DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the Applicants' file on 5/14/25. In virtue of this filing, claims 1-20 are currently presented in the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/14/25 is in compliance with the provisions of 37 CFR 1.97 &1.98. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Instant Application No:19/208,485.
1. An impedance matching network comprising:
an input; an output; a first electronically variable capacitor (EVC) coupled directly or indirectly to the input to enable receipt of an RF signal from an RF source; a second EVC, wherein the first and second EVCs do not have two common nodes; and a control circuit configured to: determine, based on a first parameter related to the impedance matching network, the RF source, or a plasma chamber coupled directly or indirectly to the output of the impedance matching network, both: a first capacitance value or configuration (CVOC) for the first EVC; and a second CVOC for the second EVC; and generate one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC;
wherein the combined alteration of the first EVC and the second EVC causes RF power
reflected back to the RF source to decrease.
2. The impedance matching network of claim 1:
wherein each of the first EVC and the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein the first CVOC or the second CVOC is a configuration, each configuration being
indicative of an activated or deactivated state for each fixed capacitor.
3. The impedance matching network of claim 1 wherein the first CVOC or the second CVOC is a
capacitance value, the capacitance value being a numeric amount of capacitance.
4. The impedance matching network of claim 1:
wherein the RF signal has a frequency; and
wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not
altered.
5. The impedance matching network of claim 1 wherein the determination of the first CVOC and
the second CVOC comprises a determination that, of possible combinations of CVOCs for the first and second EVCs, the first CVOC and the second CVOC together are most likely to achieve an impedance match.
6. The impedance matching network of claim 1 wherein the alteration of the first EVC and the
second EVC occur simultaneously.
7. The impedance matching network of claim 1 wherein the control circuit does not determine the first CVOC or the second CVOC based on an error value indicative of reflected power.
8. The impedance matching network of claim 1:
wherein the control circuit is further configured to repeat the determining the first and
second CVOCs and generating the one or more control signals to alter the first and second EVCs
to cause an impedance match; and wherein the repeated determinations of the first and second CVOCs by the control circuit are not based on bringing an error signal indicative of reflected power to zero.
9. The impedance matching network of claim 1:
wherein the RF signal has a frequency; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not altered; and wherein the alteration of the first and second EVCs causes the RF power reflected back to the RF source to begin decreasing with 150 usec of the determination of the first parameter.
10. The impedance matching network of claim 1:
wherein the RF signal has a frequency; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not altered; wherein the steps of determining the first and second CVOCs and generating the one or more control signals to alter the first and second EVCs are repeated to cause an impedance match; and wherein the impedance match is caused in an elapsed time of 500 usec or less.
11. The impedance matching network of claim 1:
wherein the second EVC comprises a plurality of fixed capacitors, each fixed capacitor
having a corresponding switch to activate or deactivate the fixed capacitor; and wherein each corresponding switch comprises a plurality of PiN or NiP diodes coupled in series.
12. The impedance matching network of claim 1 wherein the first parameter is determined using
a look-up table.
13. The impedance matching network of claim 1:
wherein the first parameter is a variable impedance of the plasma chamber; and
wherein the variable impedance of the plasma chamber is determined based on either a
parameter detected by a sensor positioned at the RF input or a parameter detected by a sensor at
the RF output.
14. The impedance matching network of claim 1 wherein there is no fixed impedance matching
section coupled between the RF output and the plasma chamber.
15. A method for impedance matching, the method comprising: coupling an impedance matching network between an RF source having a fixed impedance and a plasma chamber, the impedance matching network comprising:
a first electronically variable capacitor (EVC) coupled directly or indirectly to an input of the impedance matching network to enable receipt of an RF signal from an RF source; a second EVC, wherein the first and second EVCs do not have two common nodes; determining, based on a first parameter related to the impedance matching network, the RF source, or the plasma chamber, both: a first capacitance value or configuration (CVOC) for the first EVC; and
a second CVOC for the second EVC; and
altering the first EVC to the first CVOC and the second EVC to the second CVOC.
16. The method of claim 15: wherein each of the first EVC and the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein the first CVOC or the second CVOC is a configuration, each configuration being indicative of an activated or deactivated state for each fixed capacitor.
17. The method of claim 15: wherein the RF signal has a frequency; and wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not altered.
18. The method of claim 15 wherein the alteration of the first EVC and the second EVC occur simultancously.
19. The method of claim 15 wherein the control circuit does not determine the first CVOC or the
second CVOC based on an error value indicative of reflected power.
20. A semiconductor processing tool comprising:
a plasma chamber configured to deposit a material onto a substrate or etch a material from
the substrate; and an impedance matching network operably coupled to the plasma chamber, the impedance matching network comprising: an input; an output operably coupled to the plasma chamber; a first electronically variable capacitor (EVC) coupled directly or indirectly to the input to enable receipt of an RF signal from an RF source; a second EVC, wherein the first and second EVCs do not have two common nodes; and a control circuit configured to: determine, based on a first parameter related to the impedance matching
network, the RF source, or the plasma chamber, both: a first capacitance value or configuration (CVOC) for the first EVC; and a second CVOC for the second EVC; and generate one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC;
wherein the combined alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease.
Patent No: 12334306.
1. A radio frequency (RF) impedance matching circuit comprising: an RF input configured to operably couple to an RF source and to receive an RF signal at a first frequency from the RF source, the RF source having a fixed output impedance; an RF output configured to operably couple to a plasma chamber; a first electronically variable capacitor (EVC) coupled to the RF input to receive the RF signal from the RF source at the first frequency; a second EVC separate and distinct from the first EVC, the second EVC coupled to the RF input to receive the RF signal from the RF source at the first frequency, wherein the first EVC has two terminals, the second EVC has two terminals, and the two terminals of the first EVC are not both common to the two terminals of the second EVC; and a control circuit operably coupled to the first and second EVCs and configured to: determine a first parameter related to the plasma chamber, the matching circuit, or the RF source; determine, based on the first parameter, both: a first capacitance value or configuration (CVOC) for the first EVC; and a second CVOC for the second EVC; and generate one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease.
2. The RF impedance matching circuit of claim 1 wherein the first CVOC or the second CVOC is a capacitance value, the capacitance value being a numeric amount of capacitance.
3. The RF impedance matching circuit of claim 1: wherein each of the first EVC and the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein the first CVOC or the second CVOC is a configuration, each configuration being indicative of an activated or deactivated state for each fixed capacitor.
4. The RF impedance matching circuit of claim 1 wherein the first EVC and the second EVC are not in parallel.
5. The RF impedance matching circuit of claim 1: wherein the RF signal has a frequency; and wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the first frequency of the RF signal from the RF source is not altered.
6. The RF impedance matching circuit of claim 1 wherein the determination of the first CVOC and the second CVOC comprises a determination that, of possible combinations of CVOCs for the first and second EVCs, the first CVOC and the second CVOC together are most likely to achieve an impedance match.
7. The RF impedance matching circuit of claim 1 wherein the alteration of the first EVC and the second EVC occur simultaneously.
8. The RF impedance matching circuit of claim 1 wherein the control circuit does not determine the first CVOC or the second CVOC based on an error value indicative of reflected power.
9. The RF impedance matching circuit of claim 1: wherein the control circuit is further configured to repeat the determining the first and second CVOCs and generating the one or more control signals to alter the first and second EVCs to cause an impedance match; and wherein the repeated determinations of the first and second CVOCs by the control circuit are not based on bringing an error signal indicative of reflected power to zero.
10. The RF impedance matching circuit of claim 1: wherein the RF signal has a frequency; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the first frequency of the RF signal from the RF source is not altered; and wherein the alteration of the first and second EVCs causes the RF power reflected back to the RF source to begin decreasing with 150 μsec of the determination of the first parameter.
11. The RF impedance matching circuit of claim 1: wherein the RF signal has a frequency; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the first frequency of the RF signal from the RF source is not altered; wherein the steps of determining the first and second CVOCs and generating the one or more control signals to alter the first and second EVCs are repeated to cause an impedance match; and wherein the impedance match is caused in an elapsed time of 500 μsec or less.
12. The RF impedance matching circuit of claim 1: wherein the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein each corresponding switch comprises a plurality of PiN or NiP diodes coupled in series.
13. The RF impedance matching circuit of claim 1 wherein the first parameter is determined using a look-up table.
14. The RF impedance matching circuit of claim 1 wherein the first parameter is a variable impedance of the plasma chamber.
15. The RF impedance matching circuit of claim 14 wherein the variable impedance of the plasma chamber is determined based on either a parameter detected by a sensor positioned at the RF input or a parameter detected by a sensor at the RF output.
16. The RF impedance matching circuit of claim 1 wherein the RF output is coupled directly to the plasma chamber.
17. The RF impedance matching circuit of claim 1 wherein there is no fixed impedance matching section coupled between the RF output and the plasma chamber.
18. A method for radio frequency (RF) impedance matching, the method comprising: coupling an RF impedance matching circuit between an RF source having a fixed impedance and a plasma chamber, the matching circuit comprising: a first electronically variable capacitor (EVC) coupled to an RF input of the matching circuit to receive an RF signal from an RF source at a first frequency; and a second EVC separate and distinct from the first EVC, the second EVC coupled to the RF input to receive the RF signal from the RF source at the first frequency, wherein the first EVC has two terminals, the second EVC has two terminals, and the two terminals of the first EVC are not both common to the two terminals of the second EVC; receiving, at the RF input of the matching circuit, the RF signal at the first frequency from the RF source; determining a first parameter related to the plasma chamber, the matching circuit, or the RF source; determining, based on the first parameter, both: a first capacitance value or configuration (CVOC) for the first EVC; and a second CVOC for the second EVC; and generating one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease.
19. The method of claim 18 wherein the first CVOC or the second CVOC is a capacitance value, the capacitance value being a numeric amount of capacitance.
20. The method of claim 18: wherein each of the first EVC and the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein the first CVOC or the second CVOC is a configuration, each configuration being indicative of an activated or deactivated state for each fixed capacitor.
21. The method of claim 18: wherein the RF signal has a frequency; and wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not altered.
22. The method of claim 18 wherein the determination of the first CVOC and the second CVOC comprises a determination that, of possible combinations of CVOCs for the first and second EVCs, the first CVOC and the second CVOC together are most likely to achieve an impedance match.
23. The method of claim 18 wherein the alteration of the first EVC and the second EVC occur simultaneously.
24. The method of claim 18 wherein the determination of the first CVOC and the second CVOC are not based on an error value indicative of reflected power.
25. The method of claim 18: further comprising repeating the steps of determining the first and second CVOCs and generating the one or more control signals to alter the first and second EVCs to cause an impedance match; and wherein the repeated determinations of the first and second CVOCs are not based on bringing an error signal indicative of reflected power to zero.
26. A semiconductor processing tool comprising: a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and an impedance matching circuit operably coupled to the plasma chamber, the matching circuit comprising: an RF input configured to operably couple to an RF source and to receive an RF signal at a frequency from the RF source, the RF source having a fixed output impedance; an RF output configured to operably couple to the plasma chamber; a first electronically variable capacitor (EVC) coupled to the RF input to receiver the RF signal from the RF source at the first frequency; a second EVC separate and distinct from the first EVC, wherein the first EVC, the second EVC coupled to the RF input to receive the RF signal from the RF source at the first frequency has two terminals, the second EVC has two terminals, and the two terminals of the first EVC are not both common to the two terminals of the second EVC; and a control circuit operably coupled to the first and second EVCs and configured to: determine a first parameter related to the plasma chamber, the matching circuit, or the RF source; determine, based on the first parameter, both (a) a first capacitance value or configuration (CVOC) for the first EVC, and (b) a second CVOC for the second EVC; and generate one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease.
27. The processing tool of claim 26 wherein the first CVOC or the second CVOC is a capacitance value, the capacitance value being a numeric amount of capacitance.
28. The processing tool of claim 26: wherein each of the first EVC and the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein the first CVOC or the second CVOC is a configuration, each configuration being indicative of an activated or deactivated state for each fixed capacitor.
29. The processing tool of claim 26 wherein the first EVC and the second EVC are not in parallel.
30. The processing tool of claim 26: wherein the RF signal has a frequency; and wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not altered.
31. The processing tool of claim 26 wherein the determination of the first CVOC and the second CVOC comprises a determination that, of possible combinations of CVOCs for the first and second EVCs, the first CVOC and the second CVOC together are most likely to achieve an impedance match.
32. The processing tool of claim 26 wherein the alteration of the first EVC and the second EVC occur simultaneously.
33. The processing tool of claim 26 wherein the control circuit does not determine the first CVOC or the second CVOC based on an error value indicative of reflected power.
34. The processing tool of claim 26: wherein the control circuit is further configured to repeat the determining the first and second CVOCs and generating the one or more control signals to alter the first and second EVCs to cause an impedance match; and wherein the repeated determinations of the first and second CVOCs by the control circuit are not based on bringing an error signal indicative of reflected power to zero.
35. The processing tool of claim 26: wherein the RF signal has a frequency; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the frequency of the RF signal from the RF source is not altered; and wherein the alteration of the first and second EVCs causes the RF power reflected back to the RF source to begin decreasing with 150 μsec of the determination of the first parameter.
36. The processing tool of claim 26: wherein the RF signal has a frequency; wherein the alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease while the first frequency of the RF signal from the RF source is not altered; wherein the steps of determining the first and second CVOCs and generating the one or more control signals to alter the first and second EVCs are repeated to cause an impedance match; and wherein the impedance match is caused in an elapsed time of 500 μsec or less.
37. The processing tool of claim 26: wherein the second EVC comprises a plurality of fixed capacitors, each fixed capacitor having a corresponding switch to activate or deactivate the fixed capacitor; and wherein each corresponding switch comprises a plurality of PiN or NiP diodes coupled in series.
38. The processing tool of claim 26 wherein the first parameter is determined using a look-up table.
39. The processing tool of claim 26 wherein the first parameter is a variable impedance of the plasma chamber.
40. The processing tool of claim 39 wherein the variable impedance of the plasma chamber is determined based on either a parameter detected by a sensor positioned at the RF input or a parameter detected by a sensor at the RF output.
41. The processing tool of claim 26 wherein the RF output is coupled directly to the plasma chamber.
42. The processing tool of claim 26 wherein there is no fixed impedance matching section coupled between the RF output and the plasma chamber.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12334306. Although the claims at issue are not identical, they are not patentably distinct from each other because of the below reasons:
All limitations of claim 1 of instant application are similar all limitations of claim 1 of Patent application above. The limitations of claim 1 of the instant application are broader to compare with the limitation of claim 1 of the Patent application above.
Limitations of claim 2 of the instant application are similar limitations of claims 1 and 4 of Patent application above.
Limitations of claim 3 of the instant application are similar limitations of claim 2 of Patent application above.
Limitations of claim 4 of the instant application are similar limitations of claim 5 od Patent 4application above.
Limitations of claim 5 of the instant application are similar limitations of claim 6 of Patent 5application above.
Limitations of claim 6 of the instant application are similar limitations of claim 7 of Patent application above.
Limitations of claim 7 of the instant application are similar limitations of claim 8 of Patent application above.
Limitations of claim 8 of the instant application are similar limitations of claim 9 of Patent application above.
Limitations of claim 9 of the instant application are similar limitations of claim 10 of Patent application above.
Limitations of claim 10 of the instant application are similar limitations of claim 11 of Patent application above.
Limitations of claim 11 of the instant application are similar limitations of claim 12 of Patent application above.
Limitations of claim 12 of the instant application are similar limitations of claim 13 of Patent application above.
Limitations of claim 13 of the instant application are similar limitations of claims 14 and 15 of Patent application above.
Limitations of claim 14 of the instant application are similar limitations of claim 17 of Patent application above.
All limitations of claim 15 of instant application are similar all limitations of claim 18 of Patent application above. The limitations of claim 15 of the instant application are broader to compare with the limitation of claim 18 of the Patent application above.
Limitations of claim 16 of the instant application are similar limitations of claim 20 of Patent application above.
Limitations of claim 17 of the instant application are similar limitations of claim 21 of Patent application above.
Limitations of claim 18 of the instant application are similar limitations of claim 23 of Patent application above.
Limitations of claim 19 of the instant application are similar limitations of claim 24 of Patent application above.
All limitations of claim 20 of instant application are similar all limitations of claim 26 of Patent application above. The limitations of claim 20 of the instant application are broader to compare with the limitation of claim 26 of the Patent application above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 15 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by BISHARA; WAHEB et al (US Patent No: 20140367043).
With respect to claim 1, BISHARA; WAHEB et al disclose in figures 1-2, an impedance matching network(110) comprising: an input; an output; a first electronically variable capacitor (EVC)(C1) coupled directly or indirectly to the input to enable receipt of an RF signal from an RF source(112); a second EVC(C2), wherein the first and second EVCs do not have two common nodes; and a control circuit (114) configured to: determine, based on a first parameter related to the impedance matching network(110), the RF source(112), or a plasma chamber coupled directly or indirectly to the output of the impedance matching network, both: a first capacitance value or configuration (CVOC) for the first EVC; and a second CVOC for the second EVC; and generate one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC; wherein the combined alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease. Paragraphs [8-9,20-29].
With respect to claim 15, BISHARA; WAHEB et al disclose in figures 1-2, 15. a method for impedance matching, the method comprising: coupling an impedance matching network (110) between an RF source having a fixed impedance and a plasma chamber, the impedance matching network comprising: a first electronically variable capacitor (EVC) (C1)coupled directly or indirectly to an input of the impedance matching network(110) to enable receipt of an RF signal from an RF source(112); a second EVC(C2), wherein the first and second EVCs do not have two common nodes; determining, based on a first parameter related to the impedance matching network(110), the RF source(112), or the plasma chamber(101), both: a first capacitance value (C1) or configuration (CVOC) (2) for the first EVC; and a second CVOC for the second EVC; and altering the first EVC to the first CVOC and the second EVC to the second CVOC. Paragraphs [7-8,20-29].
With respect to claim 20, BISHARA; WAHEB et al disclose in figures 1-2, 20, a semiconductor processing tool comprising: a plasma chamber (101)configured to deposit a material onto a substrate or etch a material from the substrate; and an impedance matching network (110) operably coupled to the plasma chamber(101), the impedance matching network (110)comprising: an input; an output operably coupled to the plasma chamber(101); a first electronically variable capacitor (EVC) (C1)coupled directly or indirectly to the input to enable receipt of an RF signal from an RF source(112); a second EVC(C2), wherein the first and second EVCs do not have two common nodes; and a control circuit (114) configured to: determine, based on a first parameter related to the impedance matching network, the RF source(112), or the plasma chamber(101), both: a first capacitance value (C1) or configuration (CVOC) for the first EVC; and a second CVOC (C2) for the second EVC; and generate one or more control signals to alter the first EVC to the first CVOC and the second EVC to the second CVOC; wherein the combined alteration of the first EVC and the second EVC causes RF power reflected back to the RF source to decrease. Paragraphs [7-8,20-29].
Citation of pertinent prior art
The prior art made of record and not relied upon is considered pertinent to applicants' disclosure. See prior arts/references listed on the PTO-892 form attached.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH TRAN whose telephone number is (571)272-1817. The examiner can normally be reached on 8:00 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taningco Alexander H can be reached on 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Minh Tran/
Primary Examiner
Art Unit 2845
Prosecution Insights