DETAILED ACTION
This office action is in response to the application filed on 05/15/2025. Claims 1-10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 05/15/2025 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/15/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9-10 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Salerno et al. (US Patent or PG Pub. No. 7030596, hereinafter ‘596).
Claim 1, ‘596 teaches a power supply controller configured to control an output circuit of a switching power supply that generates an output voltage from an input voltage (e.g., see Fig. 2, 5), comprising: an error amplifier (e.g., 54) configured to generate an error signal according to an error between a feedback voltage (e.g., Vfb) corresponding to the output voltage and a predetermined reference voltage (e.g., Vref, see Fig. 2); a current sensor (e.g., 14, or 52/50) configured to generate a current detection signal according to a coil current flowing through the output circuit (e.g., see Fig. 2); a duty signal generation circuit (e.g., the circuits comprising 44, Logic Gates) configured to generate a duty signal upon receiving the error signal and the current detection signal (e.g., see Fig. 2); and a drive signal generation circuit (e.g., the circuits comprising Logic Gates, 40, 42) configured to generate a drive signal for the output circuit upon receiving the duty signal (e.g., see Fig. 2), wherein the error amplifier is configured to be capable of being switched between a first mode and a second mode in response to a mode switching signal (e.g., MODE), and is configured to, in the first mode, generate the error signal using an integral voltage obtained by integrating a difference value obtained by subtracting the reference voltage from the feedback voltage (e.g., when 74 being closed), and in the second mode, generate the error signal without using the integral voltage (e.g., when 74 being open, see Fig. 2).
Claim 9, ‘596 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the mode switching signal is set by external input to a dedicated terminal, serial communication, or writing to a memory or a register (e.g., the dedicated input terminal of 74 and the control signal received from MODE, see Fig. 2, 5).
Claim 10, ‘596 teaches switching power supply, comprising: the power supply controller of Claim 1; and the output circuit (e.g., see Fig. 2, 5).
Claims 1, 5, 9, 10 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Qiu et al (US Patent or PG Pub. No. 20110062926, hereinafter ‘926).
Claim 1, ‘926 teaches a power supply controller configured to control an output circuit of a switching power supply that generates an output voltage from an input voltage (e.g., see Fig. 2, 4), comprising: an error amplifier (e.g., 206) configured to generate an error signal according to an error between a feedback voltage (e.g., Vfb) corresponding to the output voltage and a predetermined reference voltage (e.g., Vref1, see Fig. 2); a current sensor configured to generate a current detection signal according to a coil current (e.g., I2) flowing through the output circuit; a duty signal generation circuit (e.g., the circuits comprising 236, 234, 210, 228) configured to generate a duty signal upon receiving the error signal and the current detection signal; and a drive signal generation circuit (e.g., 262, 264) configured to generate a drive signal for the output circuit upon receiving the duty signal, wherein the error amplifier is configured to be capable of being switched between a first mode and a second mode in response to a mode switching signal (e.g., the output of 234/236, see [0019], Fig. 2) , and is configured to, in the first mode, generate the error signal using an integral voltage obtained by integrating a difference value obtained by subtracting the reference voltage from the feedback voltage, and in the second mode, generate the error signal without using the integral voltage (e.g., the respective output of 234 corresponding to the output of 234/236, see [0019], Fig. 2).
Claim 5, ‘926 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the error amplifier includes: an amplifier including a non-inverting input terminal (e.g., input “+“ of 206) connected to a terminal for applying the reference voltage, an inverting input terminal (e.g., input “-“ of 206) connected to a terminal for applying the feedback voltage, and an output terminal connected to a terminal (e.g., at node 209) for applying the error signal (e.g., see Fig. 2); a resistor (e.g., 216) connected between the terminal for applying the feedback voltage and a terminal (e.g., 208) for applying a node voltage (e.g., voltage of 209 through 208) see Fig. 2); a capacitor (e.g., 218 or 214) connected between the terminal for applying the node voltage and the terminal for applying the error signal; and a switch (e.g., 208) connected between the terminal for applying the node voltage and the terminal for applying the error signal and configured to be turned on and off in response to the mode switching signal (e.g., see Fig. 2).
Claim 9, ‘926 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the mode switching signal is set by external input (e.g., 234/236) to a dedicated terminal, serial communication (e.g., Loop), or writing to a memory or a register.
Claim 10, ‘926 teaches the switching power supply (e.g., 102, 200), comprising: the power supply controller of Claim 1; and the output circuit (e.g., see Fig. 1, 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103(a) as being unpatentable over Qiu et al (US Patent or PG Pub. No. 20110062926, hereinafter ‘926), in view of Wu (US Patent or PG Pub. No. 20250175083, hereinafter ‘083).
Claim 2, ‘926 teaches the limitations of claim 1 as discussed above. ‘926 further disclose that wherein the comparator (e.g., 210) configured to compare the control voltage with a ramp voltage (e.g., 232, Vref2 being a voltage "ramp" when operating in PWM mode, see [0020], Fig. 2) to generate the duty signal (e.g., the signal at 261 being PWM signal when operating in PWM mode, see [0020], Fig. 2).
‘929 does not explicitly disclose that wherein the duty signal generation circuit includes an output feedback amplifier configured to receive the error signal and the current detection signal to generate a control voltage according to the error signal and the current detection signal.
‘083 discloses a buck converter based power supply with a control circuit having a duty signal generation circuit (e.g., see Fig. 2, 5) includes an output feedback amplifier configured to receive its error signal (e.g., the output of 103, Vea) and its current detection signal (e.g., the output of 1011) to generate a control voltage (e.g., the output of the Summing circuit Vos) according to the error signal and the current detection signal in order to generate the PWM signal (e.g., see [0027], [0044]-[0047], Fig. 2, 5).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Jayaraj by including the output feedback amplifier (i.e., the summing the received the error signal and current detection signal as taught by ‘083 in order of being able to control the duty cycle of the power converter cost-effectively (e.g., see [0007][0027][0076], Fig. 2)
Allowable Subject Matter
Claims 3-4, 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claims 3-4, 6-8, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a second amplifier including a first non-inverting input terminal connected to the terminal for applying the reference voltage, a first inverting input terminal connected to the terminal for applying the feedback voltage, a second non-inverting input terminal connected to the terminal for applying the integral voltage, a second inverting input terminal connected to a terminal for applying a node voltage, and an output terminal connected to a terminal for applying the error signal; a first resistor connected between a terminal for applying a bias voltage and the terminal for applying the node voltage; a second resistor connected between the terminal for applying the node voltage and the terminal for applying the error signal; a capacitor connected between the terminal for applying the integral voltage and a reference potential terminal or between the terminal for applying the integral voltage and the terminal for applying the bias voltage; and a switch connected between the terminal for applying the integral voltage and the terminal for applying the bias voltage and configured to be turned on and off in response to the mode switching signal”.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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