Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Na et al., US 2020/0168147 A1, hereinafter “Na”.
Regarding claim 1, Na teaches a display substrate (fig. 3, ¶ 121), comprising a base substrate (fig. 3, element 110, ¶ 121) and a plurality of subpixels arranged in an array form on the base substrate (¶ 166), wherein the plurality of subpixels is arranged in rows (per ¶ 166 pixels are arranged in matrix form, fig. 1 further teaches two pixels in a row); each subpixel comprises a subpixel driving circuitry (figs. 1 and 4), the subpixel driving circuitry comprises a driving transistor (T1, ¶ 50) and a first transistor (T3, ¶ 50), a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor is coupled to a gate electrode of the driving transistor (see fig. 4), and an active layer of the first transistor comprises a first semiconductor portion and a second semiconductor portion spaced apart from each other (fig. 1, see T3-1 and T3-2; ¶ 65), and a conductor portion coupled to the first semiconductor portion and the second semiconductor portion (fig. 1, N3, ¶ 65); wherein each subpixel further comprises a power source signal line (fig. 1, line 172), at least a part of the power source signal line extends in a second direction, and a voltage stabilizing electrode is coupled to the power source signal line (¶ 133); and the voltage stabilizing electrode comprises a first portion (¶ 104, at least portions of M3) and a second portion (¶ 104, M1 and M2, overlapping portion and the extended portion) coupled to each other, wherein the display substrate further comprises a data line (fig. 1, line 171), wherein the subpixel driving circuitry further comprises a data write-in transistor (fig. 4, T2, ¶ 50), a gate electrode of which is coupled to the gate line, a first electrode of which is coupled to the data line, a second electrode of which is coupled to the first electrode of the driving transistor (see T2 in figs. 1 and 4), and the first electrode of the data write-in transistor is integrated in the active layer of the first transistor (fig. 2, ¶ 55, S2 is integrated in the semiconducting layer); wherein the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the first electrode of the data write-in transistor onto the base substrate (¶ 76: shield layer M may overlap first electrode S2), and the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the data line onto the base substrate (fig. 2, ¶ 75, at least a portion of M2 overlaps the data line as M is arranged between two adjacent pixels), and the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the first transistor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line (fig. 2, see the M1/M2 portion between the coupling 62 and T3. Furthermore, note that portions of M3 can also be identified as the second portion which would fall between T3 and coupling point 62), wherein a second portion of a voltage stabilizing electrode in the last column only occludes a first electrode of a data write-in transistor of a subpixel driving circuitry in the last column, and a second portion of a voltage stabilizing electrode in remaining columns obscures a first electrode of a data write-in transistor of a subpixel driving circuitry in its own column and a conductor portion of a first transistor of a subpixel driving circuitry in its next column (fig. 1 and 2, M1 and M2 portions which are considered to be at least portions of the second portion of the voltage stabilizing electrode, only obscure the Dm line which is a first electrode of data write-in transistor (fig. 4, T2) in the column of P1, while in the P2 column such obstruction occurs over the first electrode of T2 in P2 and a conductor portion N3 of P1).
Regarding claim 2, Na teaches that the subpixel driving circuitry further comprises a first conductive connection member (fig. 1, first data connection member 71, ¶ 94), the first conductive connection member extends along the second direction (see fig. 1), an orthogonal projection of the second electrode of the first transistor onto the base substrate overlaps an orthogonal projection of a first end of the first conductive connection member onto the base substrate at a first overlapping region (D3 overlaps the first end of 71), the second electrode of the first transistor is coupled to the first end of the first conductive connection member at the first overlapping region (¶ 94, connection hole 63), a second end of the first conductive connection member is coupled to the gate electrode of the driving transistor (¶ 94, connection hole 61), and the orthogonal projection of the first portion onto the base substrate is located between an orthogonal projection of the first overlapping region onto the base substrate and an orthogonal projection of the data line onto the base substrate (see fig. 1).
Regarding claim 3, Na teaches that the orthogonal projection of the data line onto the base substrate is located between an orthogonal projection of a channel portion of the data write-in transistor onto the base substrate and the orthogonal projection of the conductor portion of the first transistor of a next subpixel onto the base substrate (see fig. 1, wherein data line 171 of P2 is between the channel portion of T2 of P2 and N3 of P1).
Regarding claim 4, Na teaches that each subpixel further comprises a data line (fig. 1, 171), and at least a part of the data line extends in a second direction intersecting the first direction, wherein the subpixel driving circuitry further comprises: a second conductive connection member (fig. 1, third data connection member 73, ¶ 90), at least a part of the second conductive connection member extending along the second direction (see fig. 1); a second transistor (fig. 4, T4), a gate electrode of which is coupled to a resetting signal line (Sn-1, ¶ 69), a first electrode of which is coupled to an initialization signal line (Vint), and a second electrode of which is coupled to the second electrode of the first transistor (see fig. 4); and a seventh transistor (fig. 4, T7), a gate electrode of which is coupled to a resetting signal line of a next subpixel in the second direction (gate is connected to the previous scan line which is a resetting line of a next pixel in the second direction, see ¶ 90), and a first electrode of which is coupled to an initialization signal line of the next subpixel in the second direction (fig. 1, Vint line 128 which carries a constant voltage for the whole matrix), and a second electrode of which is coupled to an anode of a corresponding light-emitting element (fig. 4, T7 configuration), wherein an orthogonal projection of a channel portion of the second transistor onto the base substrate is located between the orthogonal projection of the data line onto the base substrate and an orthogonal projection of the second conductive connection member onto the base substrate (see fig. 1), and an orthogonal projection of a channel portion of the seventh transistor onto the base substrate is located between the orthogonal projection of the second conductive connection member coupled to the seventh transistor (coupled through hole 67, ¶ 90) onto the base substrate and an orthogonal projection of the data line of a previous subpixel of the subpixel to which the seventh transistor belongs in the first direction onto the base substrate (see fig. 1).
Regarding claim 5, Na teaches that the subpixel driving circuitry further comprises: a fifth transistor (fig. 4, T5), a gate electrode of which is coupled to a light-emission control signal line (EM), a first electrode of which is coupled to the power source signal line (ELVDD), and a second electrode of which is coupled to the first electrode of the driving transistor (D5 to S1); and a sixth transistor (fig. 4, T6), a gate electrode of which is coupled to the light-emission control signal line (EM), a first electrode of which is coupled to the second electrode of the driving transistor (S6 to D1), and a second electrode of which is coupled to an anode of a light-emitting element (see fig. 4, T6 and OLED configuration), wherein an orthogonal projection of a channel portion of the fifth transistor onto the base substrate is located between the orthogonal projection of the data line onto the base substrate and an orthogonal projection of the power source signal line onto the base substrate (fig. 1, channel portion of T5 is between lines 171 and 172), and an orthogonal projection of a channel portion of the sixth transistor onto the base substrate is located between the orthogonal projection of a second conductive connection member coupled to the sixth transistor onto the base substrate and an orthogonal projection of the data line of a previous subpixel of the subpixel to which the sixth transistor belongs in the first direction onto the base substrate (fig. 1, channel portion of T6 is between 74 and 171 of P2).
Regarding claim 6, Na teaches that an orthogonal projection of the first electrode of the driving transistor onto the base substrate is located between an orthogonal projection of the gate electrode of the driving transistor onto the base substrate and the orthogonal projection of the data line onto the base substrate (S1 is between projection of gate and data line 171), and an orthogonal projection of the second electrode of the driving transistor onto the base substrate is located between the orthogonal projection of the gate electrode of the driving transistor onto the base substrate and an orthogonal projection of the data line of a previous subpixel of the subpixel to which the driving transistor belongs in the first direction onto the base substrate (D1 is between the gate and data line 171 of P2).
Regarding claim 7, Na teaches that the subpixel driving circuitry further comprises a storage capacitor (fig. 4, Cst), a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor (E1 to G1), a second electrode plate of the storage capacitor is coupled to the power source signal line (E2 to ELVDD), and the voltage stabilizing electrode and the second electrode plate of the storage capacitor are arranged at a same layer and made of a same material (¶ 80, M is on the same layer and material as 124 which is E2 per ¶ 59), the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the storage capacitor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line (the M1 portion is between the coupling 62 and storage electrode 124. Furthermore, note that portions of M3 can also be identified as the second portion which would fall between storage electrode 124 and coupling point 62).
Regarding claim 8, Na teaches that each subpixel further comprises: a data line, at least a part of the data line extending in a second direction intersecting the first direction (fig. 1, 171); and a power source signal line (fig. 1, line 172), wherein at least a part of the power source signal line extending in the second direction, an orthogonal projection of the second electrode plate of the storage capacitor onto the base substrate overlaps the orthogonal projection of the power source signal line onto the base substrate at a second overlapping region where the second electrode of the storage capacitor is coupled to the power source signal line (see fig. 1, ¶ 92, connection hole 69), and the orthogonal projection of the data line onto the base substrate is located between an orthogonal projection of the first overlapping region onto the base substrate and an orthogonal projection of the gate electrode of the driving transistor of a next subpixel of the subpixel to which data line belongs in the first direction onto the base substrate (data line 171 of P2 is between N3 of P2 and gate projection of P1).
Regarding claim 9, Na teaches that the subpixel driving circuitry (see fig. 4) comprises: a first transistor (T3), a gate electrode of which is coupled to the gate line (151); a second transistor (T4), a gate electrode of which is coupled to a resetting signal line (line 152, Sn-1 provides the resetting signal), a first electrode of which is coupled to an initialization signal line (127), and a second electrode of which is coupled to the second electrode of the first transistor (D4 to D3-1); a data write-in transistor (T2), a gate electrode of which is coupled to the gate line (151), a first electrode of which is coupled to the data line (171), and a second electrode of which is coupled to the first electrode of the driving transistor (D2 to S1); a fifth transistor (T5), a gate electrode of the which is coupled to a light-emission control signal line (EM), a first electrode of which is coupled to the power source signal line (ELVDD), and a second electrode of which is coupled to the first electrode of the driving transistor (D5 to S1); a sixth transistor (T6), a gate electrode of which is coupled to the light-emission control signal line (EM), a first electrode of which is coupled to the second electrode of the driving transistor (S6 to D1), and a second electrode of which is coupled to an anode of a light-emitting element (D6 to anode of OLED); a seventh transistor (T7), a gate electrode of which is coupled to a resetting signal line of a next subpixel in the second direction (¶ 52, connection to Sn-1 which is a resetting signal line of a next subpixel in the next row which is in the second direction), and a first electrode of which is coupled to an initialization signal line of the next subpixel in the second direction (128 which carries the initialization signal which is a constant voltage provided to all subpixels), and a second electrode of which is coupled to the anode of the corresponding light-emitting element (S7 to anode of OLED); and a storage capacitor (Cst), a first electrode plate of which is coupled to the gate electrode of the driving transistor (E1 to G1), and a second electrode plate of which is coupled to the power source signal line (E2 to ELVDD line 172).
Regarding claim 10, Na teaches that the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the first transistor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line comprises: the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of a first transistor of a subpixel driving circuitry in (I+1)th column onto the base substrate and an orthogonal projection of a coupling position of a first electrode of a data write-in transistor of a subpixel driving circuitry in Ith column and the data line, wherein I is equal to or greater than 1, and I+1 is less than or equal to N (the M1 portion is between the coupling 62 and T3. Note that portions of M3 can also be identified as the second portion which would fall between T3 and coupling point 62. Furthermore, note that the pixel circuit of fig. 1 is repeated in the row direction based on which the M1 portion would fall between the coupling 62 of the ith pixel and the T3 of the i+1th pixel in the next column).
Regarding claim 11, Na teaches a display device (¶ 48, OLED display), comprising the display substrate according to claim 1 (see rejection of claim 1 above).
Regarding claims 12-15, limitations similar to claims 2-5 have been recited. Accordingly claims 12-15 are rejected similarly to claims 2-5 as provided above.
Regarding claim 16, Na teaches a method for manufacturing a display substrate of claim 1 (see rejection of claim 1 above).
Regarding claim 18, Na teaches that the subpixel driving circuitry comprises a storage capacitor (fig. 4, Cst), a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor (E1 to G1), a second electrode plate of the storage capacitor is coupled to the power source signal line (E2 to ELVDD line 172), wherein the voltage stabilizing electrode and the second electrode plate of the storage capacitor at a same layer and made of a same material (per ¶ 59 and 80, E2 and M are formed on the same layer and have a same material (conductive material)).
Regarding claim 19, Na teaches that the orthogonal projection of the data line onto the base substrate is located between an orthogonal projection of a channel portion of the data write-in transistor onto the base substrate and the orthogonal projection of the conductor portion of the first transistor of a next subpixel onto the base substrate (see fig. 1, wherein data line 171 of P2 is between the channel portion of T2 of P2 and N3 of P1).
Regarding claim 20, Na teaches that the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the first transistor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line comprises: the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of a first transistor of a subpixel driving circuitry in (I+1)th column onto the base substrate and an orthogonal projection of a coupling position of a first electrode of a data write-in transistor of a subpixel driving circuitry in Ith column and the data line, wherein I is equal to or greater than 1, and I+1 is less than or equal to N (the M1 portion is between the coupling 62 and T3. Note that portions of M3 can also be identified as the second portion which would fall between T3 and coupling point 62. Furthermore, note that the pixel circuit of fig. 1 is repeated in the row direction based on which the M1 portion would fall between the coupling 62 of the ith pixel and the T3 of the i+1th pixel in the next column).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Na, in view of Xin et al., US 2019/0035875 A1, hereinafter “Xin”.
Regarding claim 17, Na teaches that the subpixel driving circuitry comprises a storage capacitor (fig. 4, Cst), and a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor (E1 to G1), and a second electrode plate of the storage capacitor is coupled to the power source signal line (E2 to ELVDD line 172), wherein the forming the plurality of subpixels arranged in an array form on the base substrate comprises forming the voltage stabilizing electrode and the second electrode plate of the storage capacitor on the same layer (per ¶ 59 and 80, E2 and M are formed on the same layer).
Na does not specifically teach forming the voltage stabilizing electrode and the second electrode plate of the storage capacitor simultaneously through a single patterning process.
Xin, however, clearly teaches in ¶ 30 and 36 that electrodes that are formed on the same layer “can be manufactured through a same patterning process”.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Na and Xin to form the voltage stabilizing electrode and the second electrode plate of the storage capacitor simultaneously through a single patterning process. One would have been motivated to make such a combination since Xin clearly teaches that such patterning process saves the number of required processes to form different electrodes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12336290, hereinafter “the patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of the patent teach every limitation of the claims of the instant application.
Instant application
The patent
1. A display substrate, comprising a base substrate and a plurality of subpixels arranged in an array form on the base substrate, wherein the plurality of subpixels is arranged in rows;
each subpixel comprises a subpixel driving circuitry, the subpixel driving circuitry comprises a driving transistor and a first transistor, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor is coupled to a gate electrode of the driving transistor, and an active layer of the first transistor comprises a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to the first semiconductor portion and the second semiconductor portion; wherein each subpixel further comprises a power source signal line, at least a part of the power source signal line extends in a second direction, and a voltage stabilizing electrode is coupled to the power source signal line; and the voltage stabilizing electrode comprises a first portion and a second portion coupled to each other,
wherein the display substrate further comprises a data line,
wherein the subpixel driving circuitry further comprises a data write-in transistor, a gate electrode of which is coupled to the gate line, a first electrode of which is coupled to the data line, a second electrode of which is coupled to the first electrode of the driving transistor, and the first electrode of the data write-in transistor is integrated in the active layer of the first transistor; wherein the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the first electrode of the data write-in transistor onto the base substrate, and the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the data line onto the base substrate, and the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the first transistor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line,
wherein a second portion of a voltage stabilizing electrode in the last column only occludes a first electrode of a data write-in transistor of a subpixel driving circuitry in the last column, and a second portion of a voltage stabilizing electrode in remaining columns obscures a first electrode of a data write-in transistor of a subpixel driving circuitry in its own column and a conductor portion of a first transistor of a subpixel driving circuitry in its next column.
1. A display substrate, comprising a base substrate and a plurality of subpixels arranged in an array form on the base substrate, wherein the plurality of subpixels is arranged in rows, and each row of subpixels comprises N subpixels arranged in sequence along a first direction, where N is a positive integer;
each subpixel comprises a subpixel driving circuitry, the subpixel driving circuitry comprises a driving transistor and a first transistor, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor is coupled to a gate electrode of the driving transistor, and an active layer of the first transistor comprises a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to the first semiconductor portion and the second semiconductor portion; wherein each subpixel further comprises a power source signal line, at least a part of the power source signal line extends in a second direction, and a voltage stabilizing electrode is coupled to the power source signal line; and the voltage stabilizing electrode comprises a first portion and a second portion coupled to each other, an orthogonal projection of the first portion onto the base substrate overlaps an orthogonal projection of the power source signal line onto the base substrate at an overlapping region where the first portion is coupled to the power source signal line, at least a part of the second portion extends along the first direction to a next subpixel in the first direction, and an orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of a second portion of a voltage stabilizing electrode of a previous subpixel of the subpixel to which the conductor portion belongs in the first direction onto the substrate; and the voltage stabilizing electrode is L-shaped,
wherein each subpixel further comprises a data line, and at least a part of the data line extends in a second direction intersecting the first direction,
wherein the subpixel driving circuitry further comprises a data write-in transistor, a gate electrode of which is coupled to the gate line, a first electrode of which is coupled to the data line, and a second electrode of which is coupled to the first electrode of the driving transistor,
wherein the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the first electrode of the data write-in transistor onto the base substrate, and the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the data line onto the base substrate, and the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the first transistor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line, the plurality of subpixels arranged in rows comprises red subpixels, blue subpixels and green subpixels, and are arranged in a diamond shape, in each row, a red subpixel, a green subpixel, a blue subpixel, and a green subpixel are arranged sequentially, in the first direction, subpixels at a first column are the red subpixels or the blue subpixels, subpixels at last column are the green subpixels, the first boundary is a boundary where the green subpixels are located, the voltage stabilizing electrodes stabilize subpixel driving circuitries of other subpixels except red subpixels or blue subpixels in the first column;
wherein a second portion of a voltage stabilizing electrode in the last column only occludes a first electrode of a data write-in transistor of a subpixel driving circuitry in the last column, and a second portion of a voltage stabilizing electrode in remaining columns obscures a first electrode of a data write-in transistor of a subpixel driving circuitry in its own column and a conductor portion of a first transistor of a subpixel driving circuitry in its next column; the first electrode of the data write-in transistor is integrated in the active layer of the first transistor.
2-10: Identical
2-10: Identical
11. A display device, comprising the display substrate according to claim 1.
11. A display device, comprising the display substrate according to claim 1.
12-15: Identical limitations
2-5: Identical limitations
16. A method for manufacturing the display substrate of claim 1. (Note that similar limitations as claim 1 is recited)
12. A method for manufacturing the display substrate of claim 1. (Note that similar limitations as claim 1 is recited)
17-20: Identical
13-16: Identical
Conclusion
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/SEPEHR AZARI/Primary Examiner, Art Unit 2621