DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 05/16/2025 are acceptable for examination purposes.
Information Disclosure Statement
The reference(s) listed in the disclosure statement (IDS) submitted on 05/16/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 8, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen (US 5781718 A) in view of Corso Sarmiento et al (US 20230079000 A1), herein Corso.
As per claim 1, Nguyen teaches an electronic device with an integrated circuit (Complex electronic circuits are often tested during production to make sure that they function properly. For example, LSI, VLSI, and ULSI integrated circuits are often tested on a tester during production; Nguyen Col. 1, lines 22-25):
wherein the integrated circuit has: a plurality of scan chains (For generality, the device under test could have many scan chains of different lengths and could be driven by clocks of different frequencies…device under test 52 has one or more scan inputs SCANINn and one or more scan outputs SCANOUTn; Nguyen Col.7 lines 55-64);
a clock signal source configured to provide a clock signal (Clock synchronizer 56 generates all system clocks…monitors the clock outputs of the device under test so that clocks may be stopped and restarted synchronously; Nguyen Col. 8, line 52-53)(In operation, clock synchronizer 56 generates one or more clock signals, CKINAn, for the device under test; Nguyen Col. 9, lines 28-29);
and a clock supply circuit for each group of one or more of the scan chains having a same length (The design of initialization controller 50 may depend upon whether scan chains of device under test 52 may be individually enabled or have equal length; Nguyen Col. 7, lines 50-54)(If a clock is associated with multiple scan chains having the same length, the clock may be used to clock the appropriate scan chains for that number of clock cycles; Nguyen Col. 24-27),
wherein the clock supply circuit is configured to supply the clock signal to scan flip-flops of the group of scan chains (A scan chain refers to a chain of shift register elements ("shift register elements" equates as scan flip-flops) used to access the internal state of a device's registers; Nguyen Col. 7, lines 52-55)(If a clock is associated with multiple scan chains having the same length, the clock may be used to clock the appropriate scan chains for that number of clock cycles; Nguyen Col. 8, lines 24-27)(Scan operations for scan controller 66 are controlled by clock signals generated by clock synchronizer 56; Nguyen Col. 9, lines 25-27);
wherein the clock supply circuit includes a detection circuit configured to detect, for at least one of the scan chains of the group, whether a bit sequence is completely loaded into the scan chain (a number of clock cycles, L1, equivalent to the length of the scan chain…when the first scan chain is loaded, CKINA1 could cause data to be scanned in through input SCANIN1 for L1 clock cycles; Nguyen Col. 8, lines 1-5)(Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 10, lines 3-4) and
wherein the clock supply circuit is configured to suppress the supply of clock pulse to the flip-flops of the group of scan chains (Initialization controller 50 monitors clock output signals CKOUTn and may deactivate one or more clock signals, CKINAn and/or CKINBn, synchronously in response to clock signals CKOUTn; Nguyen Col. 7, lines 25-30)(clock synchronizer 56 synchronously stops the clock inputs, CKINAn, in response to one or more clock signals, CKOUTn; Nguyen Col. 9, lines 38-43).
Nguyen does not explicitly teach an detection circuit detecting completion of loading. Nguyen also does not explicitly teach in response to the detection circuit detecting that, for the at least one of the scan chains of the group, the bit sequence has been completely loaded into the scan chain.
However, Corso in an analogous art teaches wherein the clock supply circuit includes a detection circuit configured to detect, for at least one of the scan chains of the group, whether a bit sequence is completely loaded into the scan chain (the control registers in BIST controller 130 (e.g. pattern count register and shift length register) can be set or programmed to the desired values (BIST controller and shift length register equates control circuitry that provides the claimed detection functionality)…the shift length refers to the number of clock cycles required to load the chains for each pattern…This bit pattern has a corresponding shift length…These bits are shifted into the corresponding scan chains…At decision diamond 214 it is determined whether the full shift length for the current pattern is complete…he scan chain can receive the next input bit while providing the next output bit in accordance with the next pulse of the shift clock.; Corso p. 0016-0017) and
wherein the clock supply circuit is configured to suppress the supply of clock pulse to the flip-flops of the group of scan chains in response to the detection circuit detecting that, for the at least one of the scan chains of the group, the bit sequence has been completely loaded into the scan chain (At decision diamond 214, after the shift length number of bits have been processed such that the full shift of the current test pattern is complete, at block 216, BIST controller 130 negates scan_en to disable the shift clock (thus ending the current scan phase)("suppress"); Corso p. 0018).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen with the teachings of Corso by configuring determining whether the required shift length for loading the scan patter has been completed and in response to that determination, disabling the shift clock.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ detection circuit detecting completion of loading in the system of Nguyen because Corso teaches how improved testing of clock generation circuitry can be achieved through BIST with the use of clock counters, clock gating elements, and scan chains, in which scan testing is performed through both scan and capture phases (Corso p. 0025).
As per claim 2, Nguyen in view of Corso, as combined, teaches the electronic device of claim 1, comprising
a memory which is set up to store the bit sequence (Scan controller 66 is connected to the scan inputs and scan outputs of the device under test. Scan controller 66 receives control signals from instruction decoder 60 and reads the state of the registers of the device under test from the scan output of the device under test and stores the state of those registers in RAM 68. RAM 68 serves as a buffer memory; Nguyen Col. 9, lines 19-25).
As per claim 8, Nguyen teaches a method for restoring a state of an integrated circuit, comprising:
supplying a clock signal to scan flip-flops of a plurality of scan chains (The design of initialization controller 50 may depend upon whether scan chains of device under test 52 may be individually enabled or have equal length; Nguyen Col. 7, lines 50-54)(If a clock is associated with multiple scan chains having the same length, the clock may be used to clock the appropriate scan chains for that number of clock cycles; Nguyen Col. 24-27);
and for each group of one or more of the scan chains which have the same length, detecting whether, for at least one of the scan chains of the group, a bit sequence has been completely loaded into the scan chain (a number of clock cycles, L1, equivalent to the length of the scan chain…when the first scan chain is loaded, CKINA1 could cause data to be scanned in through input SCANIN1 for L1 clock cycles; Nguyen Col. 8, lines 1-5)(Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 10, lines 3-4);
and suppressing a supply of clock pulses to the flip-flops of the group of scan chains as a response to detecting that, for at least one of the scan chains of the group, the bit sequence has been completely loaded into the scan chain (Initialization controller 50 monitors clock output signals CKOUTn and may deactivate one or more clock signals, CKINAn and/or CKINBn, synchronously in response to clock signals CKOUTn; Nguyen Col. 7, lines 25-30)(clock synchronizer 56 synchronously stops the clock inputs, CKINAn, in response to one or more clock signals, CKOUTn; Nguyen Col. 9, lines 38-43).
Nguyen does not explicitly teach an detection circuit detecting completion of loading.
However, Corso in an analogous art teaches for each group of one or more of the scan chains which have the same length, detecting whether, for at least one of the scan chains of the group, a bit sequence has been completely loaded into the scan chain (the control registers in BIST controller 130 (e.g. pattern count register and shift length register) can be set or programmed to the desired values (BIST controller and shift length register equates control circuitry that provides the claimed detection functionality)…the shift length refers to the number of clock cycles required to load the chains for each pattern…This bit pattern has a corresponding shift length…These bits are shifted into the corresponding scan chains…At decision diamond 214 it is determined whether the full shift length for the current pattern is complete…he scan chain can receive the next input bit while providing the next output bit in accordance with the next pulse of the shift clock.; Corso p. 0016-0017);
and suppressing a supply of clock pulses to the flip-flops of the group of scan chains as a response to detecting that, for at least one of the scan chains of the group, the bit sequence has been completely loaded into the scan chain (At decision diamond 214, after the shift length number of bits have been processed such that the full shift of the current test pattern is complete, at block 216, BIST controller 130 negates scan_en to disable the shift clock (thus ending the current scan phase)("suppress"); Corso p. 0018).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen with the teachings of Corso by configuring determining whether the required shift length for loading the scan patter has been completed and in response to that determination, disabling the shift clock.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ detection circuit detecting completion of loading in the system of Nguyen because Corso teaches how improved testing of clock generation circuitry can be achieved through BIST with the use of clock counters, clock gating elements, and scan chains, in which scan testing is performed through both scan and capture phases (Corso p. 0025).
As per claim 12, Nguyen in view of Corso, as combined, teaches the method of claim 8, further comprising,
as part of a pause operation, storing contents of the scan flip-flops of the at least one scan chain as respective bit sequences When an initialization controller 50 receives a signal indicating that the internal state of the device under test is to be scanned and then restored, clock synchronizer 56 synchronously stops the clock inputs, CKINAn, in response to one or more clock signals, CKOUTn. Clock synchronizer 56 also stops clock signal CKINBn in synchronization with one or more clock signals, CKOUTn.; Nguyen Col. 9 lines 35-43)(TEST-REQ is an asynchronous input signal to clock synchronizer 56 that indicates a request to suspend normal operation of DUT-NXCLK-IN. TEST-GRANT is a synchronous output indicating that DUT-NXCLK-IN has been safely stopped; Nguyen Col. 10, lines 45-50)(The design of initialization controller 50 may depend upon whether scan chains of device under test 52 may be individually enabled or have equal length. A scan chain refers to a chain of shift register elements used to access the internal state of a device's registers. For generality, the device under test could have many scan chains of different lengths and could be driven by clocks of different frequencies…device under test 52 with varying scan chain lengths and varying lengths of scan chains associated with a given clock; Nguyen Col. 7, lines 50-63)(Sequencer 58, through instruction decoder 60, next causes scan controller 66 to scan in the contents of the registers of the device under test and store the register state in RAMS 68, which serve as a buffer memory. Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 9 Lines 65 - Col 10 lines 1-4)(Scan controller 66 is connected to the scan inputs and scan outputs of the device under test. Scan controller 66 receives control signals from instruction decoder 60 and reads the state of the registers of the device under test from the scan output of the device under test and stores the state of those registers in RAM 68. RAM 68 serves as a buffer memory; Nguyen Col. 9 lines 19-25)( After the registers have been scanned under control of scan controller 66, sequencer 58 causes scan controller 66 to restore the contents of the registers of the device under test and then causes PMT controller 62 to restore the contents of the internal memory of the device under test; Nguyen Col. 10 lines 4-16).
As per claim 13, Nguyen teaches a scan chain load control system, comprising:
a scan chain comprising a plurality of scan flip-flops (A scan chain refers to a chain of shift register elements ("shift register elements" equates as scan flip-flops) used to access the internal state of a device's registers; Nguyen Col. 7, lines 52-55)(If a clock is associated with multiple scan chains having the same length, the clock may be used to clock the appropriate scan chains for that number of clock cycles; Nguyen Col. 8, lines 24-27)(Scan operations for scan controller 66 are controlled by clock signals generated by clock synchronizer 56; Nguyen Col. 9, lines 25-27);
and clock supply circuit having a clock blocking control input that receives a clock suppression signal that depends on the output of the load detection flip-flop (a number of clock cycles, L1, equivalent to the length of the scan chain…when the first scan chain is loaded, CKINA1 could cause data to be scanned in through input SCANIN1 for L1 clock cycles; Nguyen Col. 8, lines 1-5)(Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 10, lines 3-4).
Nguyen does not explicitly teach a load detection flip-flop having an input coupled to an output of the scan chain; wherein the clock suppression signal has a value that causes the clock supply circuit to suppress clock pulses to the scan flip-flops when the output of the load detection flip-flop is a specified value.
However, Corso in an analogous art teaches a load detection flip-flop having an input coupled to an output of the scan chain (the control registers in BIST controller 130 (e.g. pattern count register and shift length register) can be set or programmed to the desired values (BIST controller and shift length register equates control circuitry that provides the claimed detection functionality)…the shift length refers to the number of clock cycles required to load the chains for each pattern…This bit pattern has a corresponding shift length…These bits are shifted into the corresponding scan chains…At decision diamond 214 it is determined whether the full shift length for the current pattern is complete…he scan chain can receive the next input bit while providing the next output bit in accordance with the next pulse of the shift clock; Corso p. 0016-0017);
wherein the clock suppression signal has a value that causes the clock supply circuit to suppress clock pulses to the scan flip-flops when the output of the load detection flip-flop is a specified value (At decision diamond 214, after the shift length number of bits have been processed such that the full shift of the current test pattern is complete, at block 216, BIST controller 130 negates scan_en to disable the shift clock (thus ending the current scan phase)("suppress"); Corso p. 0018).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen with the teachings of Corso by configuring determining whether the required shift length for loading the scan patter has been completed and in response to that determination, disabling the shift clock.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ detection circuit detecting completion of loading in the system of Nguyen because Corso teaches how improved testing of clock generation circuitry can be achieved through BIST with the use of clock counters, clock gating elements, and scan chains, in which scan testing is performed through both scan and capture phases (Corso p. 0025).
Claims 3-4, 9, 11, 14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Corso in further view of Wang (US 20170115342 A1).
As per claim 3, Nguyen in view of Corso, as combined, teaches the electronic device of claim 1. The combination does not explicitly teach claim 3.
However, Wang in an analogous art teaches wherein the detection circuit is connected to an output of the at least one of the scan chains of the group and is configured to detect that the bit sequence is completely loaded into the scan chain in response to the detection circuit receiving a specified value from the output of the at least one scan chain (The gating circuit may receive the output of the final scan block in the chain. The final scan block in the chain will only generate a signal that permits the gating circuit to pass the input clock signal when the tag bits of all scan blocks in the scan chain are set to the pass value; Wang p. 0080)(acts as either a no-pass gate or a pass gate depending on the tag bit having a first binary value or a second binary value respectively; Wang p. 0077)(the N bits of an N-bit data string are loaded into the N scan blocks as respective tag bits…A token latch will generate a token signal to enable the corresponding group of scan blocks if the output of the scan blocks from each preceding scan block group in the scan chain is the second binary value; Wang p. 0079) (if any one of the scan blocks has a tag bit with the no-pass value then the output of the final scan block in the scan chain will cause the input clock signal to be gated. Once the tag bits for all scan blocks for all scan block groups in the scan chain are the pass value, the output of the final scan block of the scan chain will generate an output signal causing gating circuit 516 to pass the input clock signal; Wang p. 0035).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Wang by configuring the detection circuit to be connected to an output of the at least one of the scan chains of the group and is configured to detect that the bit sequence is completely loaded into the scan chain
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ bit sequence is completely loaded in the system of Nguyen in view of Corso because Wang teaches a single data latch can be used for each scan block while correctly counting the number of bits with the predetermined binary value over two clock cycles if needed (Wang p. 0025).
As per claim 4, Nguyen in view of Corso in further view of Wang, as combined above, teaches the electronic device of claim 3,
wherein the specified value is a binary one or a binary zero (a coding of the tag bit establishes the no-pass value as logic ‘1’ and the pass value as logic ‘0'; Wang p. 0028)
As per claim 9, Nguyen in view of Corso, as combined, teaches the method of claim 8. The combination does not explicitly teach claim 9.
However, Wang in an analogous art teaches the electronic device of claim 3 further comprising
detecting that the bit sequence has been completely loaded into the scan chain in response to detecting a specified value at an output of the scan chain (The gating circuit may receive the output of the final scan block in the chain. The final scan block in the chain will only generate a signal that permits the gating circuit to pass the input clock signal when the tag bits of all scan blocks in the scan chain are set to the pass value; Wang p. 0080)(acts as either a no-pass gate or a pass gate depending on the tag bit having a first binary value or a second binary value respectively; Wang p. 0077)(the N bits of an N-bit data string are loaded into the N scan blocks as respective tag bits…A token latch will generate a token signal to enable the corresponding group of scan blocks if the output of the scan blocks from each preceding scan block group in the scan chain is the second binary value; Wang p. 0079) (if any one of the scan blocks has a tag bit with the no-pass value then the output of the final scan block in the scan chain will cause the input clock signal to be gated. Once the tag bits for all scan blocks for all scan block groups in the scan chain are the pass value, the output of the final scan block of the scan chain will generate an output signal causing gating circuit 516 to pass the input clock signal; Wang p. 0035).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Wang by configuring the detection circuit to be connected to an output of the at least one of the scan chains of the group and is configured to detect that the bit sequence is completely loaded into the scan chain
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ bit sequence is completely loaded in the system of Nguyen in view of Corso because Wang teaches a single data latch can be used for each scan block while correctly counting the number of bits with the predetermined binary value over two clock cycles if needed (Wang p. 0025).
As per claim 11, Nguyen in view of Corso in further view of Wang, as combined, teaches the method of claim 9,
wherein the specified value is a binary one or zero (a coding of the tag bit establishes the no-pass value as logic ‘1’ and the pass value as logic ‘0'; Wang p. 0028)
As per claim 14, Nguyen in view of Corso, as combined, teaches the scan chain load control system of claim 13. The combination does not explicitly teach claim 14.
However, Wang in an analogous art teaches wherein the specified value is a binary one or zero (a coding of the tag bit establishes the no-pass value as logic ‘1’ and the pass value as logic ‘0'; Wang p. 0028).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Wang by configuring the detection circuit to be connected to an output of the at least one of the scan chains of the group and is configured to detect that the bit sequence is completely loaded into the scan chain
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ bit sequence is completely loaded in the system of Nguyen in view of Corso because Wang teaches a single data latch can be used for each scan block while correctly counting the number of bits with the predetermined binary value over two clock cycles if needed (Wang p. 0025).
As per claim 17, Nguyen in view of Corso, as combined, teaches the scan chain load control system of claim 13, comprising
a plurality of scan chains receiving clocks signals from the clock supply circuit (The design of initialization controller 50 may depend upon whether scan chains of device under test 52 may be individually enabled or have equal length; Nguyen Col. 7 lines, 51-54)( If a given clock input for device under test 52 is associated with only one scan chain, then each clock may clock the appropriate scan chain for the appropriate number of clock cycles…when the first scan chain is loaded, CKINA1 could cause data to be scanned in through input SCANIN1 for L1 clock cycles.; Nguyen Col. 7 65 - Col. 8 lines 5),
wherein for each group of scan chains having a same number of scan flip-flops (effectively lengthening scan chain 3. The result is that both chains 2 and 3 now have the same length…If a clock is associated with multiple scan chains having the same length, the clock may be used to clock the appropriate scan chains for that number of clock cycles; Nguyen Col. 8, lines 14-26) (A scan chain refers to a chain of shift register elements used to access the internal state of a device's registers; Col. 7, lines 53-55).
Nguyen in view of Corso does not explicitly teach the output of one scan chain is coupled to the load detection flip-flop.
However, Wang in an analogous art teaches the output of one scan chain is coupled to the load detection flip-flop (The gating circuit may receive the output of the final scan block in the chain. The final scan block in the chain will only generate a signal that permits the gating circuit to pass the input clock signal when the tag bits of all scan blocks in the scan chain are set to the pass value; Wang p. 0080)(During each of the input clock signal pulses SCLK_I, if any one of the scan blocks has a tag bit with the no-pass value then the output of the final scan block in the scan chain will cause the input clock signal to be gated. Once the tag bits for all scan blocks for all scan block groups in the scan chain are the pass value, the output of the final scan block of the scan chain will generate an output signal causing gating circuit 516 to pass the input clock signal; Wang p. 0035).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Wang by configuring the detection circuit to be connected to an output of the at least one of the scan chains of the group and is configured to detect that the bit sequence is completely loaded into the scan chain
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ bit sequence is completely loaded in the system of Nguyen in view of Corso because Wang teaches a single data latch can be used for each scan block while correctly counting the number of bits with the predetermined binary value over two clock cycles if needed (Wang p. 0025).
As per claim 18, Nguyen in view of Corso, as combined, teaches the scan chain load control system of claim 13. The combination does not explicitly teach claim 18.
However, Wang in an analogous art teaches the scan chain load control system of claim 13, comprising
combinatorial logic having an input coupled to an output of the load detection flip-flop, the combinatorial logic configured to output the clock suppression signal in response to the output of the load detection flip-flop having the specified value (The input clock signal SCLK_I is connected to the first input of AND gate 602 and the second input of AND gate 602 is coupled to the output of the final scan block 506-6 to form a gating circuit…Various gate mans may be used to gate or otherwise disable the input clock signal. The AND gate 602 forms a gate means for selectively gating the input clock signal in one embodiment…In another embodiment, an OR gate or one or more other logic gates may be used, while adjusting the outputs of SCLK_I and TAG6 accordingly; Wang p. 0049)(If, however, the latch circuit of any scan block is in a no-pass state then the shooting chain is interrupted causing the input clock signal 518 to be gated or otherwise disabled…if any one of the scan blocks has a tag bit with the no-pass value then the output of the final scan block in the scan chain will cause the input clock signal to be gated; Wang p. 0035)(where the loaded bit is logic ‘0’, the tag bit is set to logic ‘0’ setting the latch circuit to the pass state. Where the loaded bit is logic ‘1’, the tag bit is set to logic ‘1’ setting the latch circuit to the no-pass state; Wang p. 0032).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Wang by configuring the detection circuit to be connected to an output of the at least one of the scan chains of the group and is configured to detect that the bit sequence is completely loaded into the scan chain
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ bit sequence is completely loaded in the system of Nguyen in view of Corso because Wang teaches a single data latch can be used for each scan block while correctly counting the number of bits with the predetermined binary value over two clock cycles if needed (Wang p. 0025).
As per claim 19, Nguyen in view of Corso, as combined, teaches the scan chain load control system of claim 18,
wherein the combinatorial logic comprises an AND gate (The input clock signal SCLK_I is connected to the first input of AND gate 602 and the second input of AND gate 602 is coupled to the output of the final scan block 506-6 to form a gating circuit; Wang p. 0049)
Claims 5-7, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Corso in further view of Cannon et al (US 20090113263 A1), herein Cannon.
As per claim 5, Nguyen in view of Corso, as combined, teaches the electronic device of claim 1. The combination does not explicitly teach claim 5.
However, Cannon in an analogous art teaches the electronic device of claim 1, comprising
a control circuit configured to set the scan flip-flops of at the least one scan chain to a specified binary value (it is desirable to load a scan chain with a background pattern before loading the scan chain with an analysis pattern… the background pattern may be, for example, at least n contiguous bits of logic ones, or alternately, n contiguous bits of logic zeros ("binary value"); Cannon p. 0056), to add an inverse binary value of the specified binary value to the bit sequence (The pattern comprises a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain…at least one bit of the second logic state" which follows the background pattern of the first logic state may consist of only a single bit…number of rising edge or logic zero-to-one faults OR a number of falling edge or logic one-to-zero faults; Cannon p. 0056-0060) as a leading bit (a leading bit or bits of a loaded pattern are shifted out during the extra clock(s), and not during the normal unload process; Cannon p. 0071) to generate an expanded bit sequence, and to load the expanded bit sequence into the scan chain (The data input to the first flip-flop 302 in the scan chain is also brought out to an external pin (i.e., a Scan In (SI) pin) of the circuit. After a test (or analysis) pattern is shifted into the scan chain 314, the SE signal is brought low for one cycle, and the data outputs of the combinational logic; Cannon p. 0044) by applying the expanded bit sequence to an input of the at least one scan chain (a series of 1's and 0's at the scan inputs… the input stream should be observed on the scan output if the scan chain operates correctly.; Cannon p. 0016).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Cannon by instead of using Cannon's opposite-state single bit merely as an analysis pattern following the uniform, us it as a the leading marker of the bit sequence being loaded in Corso's scan-loading procedure.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ generate and load an expanded bit sequence and applying to an input in the system of Nguyen in view of Corso because Cannon teaches it is desirable to load a scan chain with a background pattern before loading the scan chain with an analysis pattern (Cannon p. 0056).
As per claim 6, Nguyen in view of Corso, as combined, teaches the electronic device of claim 5,
wherein the control circuit is configured to effect a pause in operation of the integrated circuit (When an initialization controller 50 receives a signal indicating that the internal state of the device under test is to be scanned and then restored, clock synchronizer 56 synchronously stops the clock inputs, CKINAn, in response to one or more clock signals, CKOUTn. Clock synchronizer 56 also stops clock signal CKINBn in synchronization with one or more clock signals, CKOUTn.; Nguyen Col. 9 lines 35-43)(TEST-REQ is an asynchronous input signal to clock synchronizer 56 that indicates a request to suspend normal operation of DUT-NXCLK-IN. TEST-GRANT is a synchronous output indicating that DUT-NXCLK-IN has been safely stopped; Nguyen Col. 10, lines 45-50)
wherein for each of the scan chains (The design of initialization controller 50 may depend upon whether scan chains of device under test 52 may be individually enabled or have equal length. A scan chain refers to a chain of shift register elements used to access the internal state of a device's registers. For generality, the device under test could have many scan chains of different lengths and could be driven by clocks of different frequencies…device under test 52 with varying scan chain lengths and varying lengths of scan chains associated with a given clock; Nguyen Col. 7, lines 50-63), the control circuit is set up to store contents of the respective scan chain as the bit sequence before the pause in operation (Sequencer 58, through instruction decoder 60, next causes scan controller 66 to scan in the contents of the registers of the device under test and store the register state in RAMS 68, which serve as a buffer memory. Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 9 Lines 65 - Col 10 lines 1-4)(Scan controller 66 is connected to the scan inputs and scan outputs of the device under test. Scan controller 66 receives control signals from instruction decoder 60 and reads the state of the registers of the device under test from the scan output of the device under test and stores the state of those registers in RAM 68. RAM 68 serves as a buffer memory; Nguyen Col. 9 lines 19-25)( After the registers have been scanned under control of scan controller 66, sequencer 58 causes scan controller 66 to restore the contents of the registers of the device under test and then causes PMT controller 62 to restore the contents of the internal memory of the device under test; Nguyen Col. 10 lines 4-16).
As per claim 7, Nguyen in view of Corso, as combined, teaches the electronic device of claim 5,
wherein the control circuit is a test control circuit configured to perform a test of the integrated circuit (Sequencer 58 generates a TEST-DONE signal that indicates to clock synchronizer 56 that the test mode is done and that the clock signals for the device under test may be restarted for normal operations; Nguyen Col. 9, lines 4-7)(generates parallel module test control signals…with the test inputs and outputs of the modules residing in the device under test…PMT controller 62 is operable to signal sequencer 58 to indicate when a parallel module test sequence has been completed; Nguyen Col. 9, lines 8-20),
wherein for each of the scan chains, the test control circuit is configured to store contents of the respective scan chain as the bit sequence (Scan controller 66 is connected to the scan inputs and scan outputs of the device under test. Scan controller 66 receives control signals from instruction decoder 60 and reads the state of the registers of the device under test from the scan output of the device under test and stores the state of those registers in RAM 68. RAM 68 serves as a buffer memory; Nguyen Col. 9 lines 19-25) before the test and store the bit sequence in the respective scan chain after the test (PMT controller 62 then causes the state of the memory of the device under test to be read out and stored in a buffer memory…Sequencer 58, through instruction decoder 60, next causes scan controller 66 to scan in the contents of the registers of the device under test and store the register state in RAMS 68, which serve as a buffer memory. Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 9 lines 55 - Col 10 lines 1-4)(After the registers have been scanned under control of scan controller 66, sequencer 58 causes scan controller 66 to restore the contents of the registers of the device under test and then causes PMT controller 62 to restore the contents of the internal memory of the device under test; Nguyen Col. 4-8).
As per claim 15, Nguyen in view of Corso, as combined, teaches the scan chain load control system of claim 13, comprising:
a memory; and a control circuit configured to (Scan controller 66 is connected to the scan inputs and scan outputs of the device under test. Scan controller 66 receives control signals from instruction decoder 60 and reads the state of the registers of the device under test from the scan output of the device under test and stores the state of those registers in RAM 68. RAM 68 serves as a buffer memory; Nguyen Col. 9, lines 19-25)(the control registers in BIST controller 130 (e.g. pattern count register and shift length register) can be set or programmed to the desired values (BIST controller and shift length register equates control circuitry that provides the claimed detection functionality; Corso p. 0016-0017)
Nguyen in view of Corso does not explicitly teach loading the plurality of scan flip-flops with an inverse of the specified value; append a bit having the specified value to a bit sequence stored in the memory to generate an expanded bit sequence; and shift the expanded bit sequence into the scan chain to load the bit sequence into the scan chain.
However, Cannon in an analogous art teaches loading the plurality of scan flip-flops with an inverse of the specified value (The pattern comprises a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain…at least one bit of the second logic state" which follows the background pattern of the first logic state may consist of only a single bit…number of rising edge or logic zero-to-one faults OR a number of falling edge or logic one-to-zero faults; Cannon p. 0056-0060);
append a bit having the specified value to a bit sequence stored in the memory to generate an expanded bit sequence (The pattern comprises a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain…at least one bit of the second logic state" which follows the background pattern of the first logic state may consist of only a single bit…number of rising edge or logic zero-to-one faults OR a number of falling edge or logic one-to-zero faults; Cannon p. 0056-0060);
and shift the expanded bit sequence into the scan chain to load the bit sequence into the scan chain (Then, a pattern is shifted through the scan chain…the number of possible hold time faults in the scan chain may be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at the output of the scan chain; Cannon p. 0058).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso with the teachings of Cannon by instead of using Cannon's opposite-state single bit merely as an analysis pattern following the uniform, us it as a the leading marker of the bit sequence being loaded in Corso's scan-loading procedure.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ generate and load an expanded bit sequence and applying to an input in the system of Nguyen in view of Corso because Cannon teaches it is desirable to load a scan chain with a background pattern before loading the scan chain with an analysis pattern (Cannon p. 0056).
As per claim 16, Nguyen in view of Corso in further view of Cannon, as combined above, teaches the scan chain load control system of claim 15, comprising
a control circuit configured to determine to pause normal operation of the scan chain (When an initialization controller 50 receives a signal indicating that the internal state of the device under test is to be scanned and then restored, clock synchronizer 56 synchronously stops the clock inputs, CKINAn, in response to one or more clock signals, CKOUTn. Clock synchronizer 56 also stops clock signal CKINBn in synchronization with one or more clock signals, CKOUTn.; Nguyen Col. 9 lines 35-43)(TEST-REQ is an asynchronous input signal to clock synchronizer 56 that indicates a request to suspend normal operation of DUT-NXCLK-IN. TEST-GRANT is a synchronous output indicating that DUT-NXCLK-IN has been safely stopped; Nguyen Col. 10, lines 45-50) (The design of initialization controller 50 may depend upon whether scan chains of device under test 52 may be individually enabled or have equal length. A scan chain refers to a chain of shift register elements used to access the internal state of a device's registers. For generality, the device under test could have many scan chains of different lengths and could be driven by clocks of different frequencies…device under test 52 with varying scan chain lengths and varying lengths of scan chains associated with a given clock; Nguyen Col. 7, lines 50-63);
and store contents of the scan flip-flops in the memory (Sequencer 58, through instruction decoder 60, next causes scan controller 66 to scan in the contents of the registers of the device under test and store the register state in RAMS 68, which serve as a buffer memory. Scan controller 66 may also indicate to sequencer 58 when scanning is completed; Nguyen Col. 9 Lines 65 - Col 10 lines 1-4)(Scan controller 66 is connected to the scan inputs and scan outputs of the device under test. Scan controller 66 receives control signals from instruction decoder 60 and reads the state of the registers of the device under test from the scan output of the device under test and stores the state of those registers in RAM 68. RAM 68 serves as a buffer memory; Nguyen Col. 9 lines 19-25)( After the registers have been scanned under control of scan controller 66, sequencer 58 causes scan controller 66 to restore the contents of the registers of the device under test and then causes PMT controller 62 to restore the contents of the internal memory of the device under test; Nguyen Col. 10 lines 4-16).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Corso in further view of Wang in further view of Cannon.
As per claim 10, Nguyen in view of Corso in further view of Wang, as combined, teaches the method of claim 9. The combination does not explicitly teach claim 10.
However, Cannon in an analogous art teaches loading the scan flip-flops of the at least one of the scan chains with bit values having an inverse value with respect to the specified value (The pattern comprises a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain…at least one bit of the second logic state" which follows the background pattern of the first logic state may consist of only a single bit…number of rising edge or logic zero-to-one faults OR a number of falling edge or logic one-to-zero faults; Cannon p. 0056-0060);
appending a bit having the specified value to the bit sequence to generate an expanded bit sequence (The pattern comprises a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain…at least one bit of the second logic state" which follows the background pattern of the first logic state may consist of only a single bit…number of rising edge or logic zero-to-one faults OR a number of falling edge or logic one-to-zero faults; Cannon p. 0056-0060)
and shifting the expanded bit sequence through the scan flip-flops of the at least one scan chains until the bit having the specified value is detected at an output of the scan chain (Then, a pattern is shifted through the scan chain…the number of possible hold time faults in the scan chain may be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at the output of the scan chain; Cannon p. 0058)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso in further view of Wang with the teachings of Cannon by instead of using Cannon's opposite-state single bit merely as an analysis pattern following the uniform, us it as a the leading marker of the bit sequence being loaded in Corso's scan-loading procedure.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ generate and load an expanded bit sequence and applying to an input in the system of Nguyen in view of Corso in further view of Wang because Cannon teaches it is desirable to load a scan chain with a background pattern before loading the scan chain with an analysis pattern (Cannon p. 0056).
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Corso in further view of Wang in further view of Agashe (US 20050055615 A1), herein Agashe.
As per claim 20, Nguyen in view of Corso in further view of Wang, as combined, teaches the scan chain load control system of claim 18,
having a Delay input coupled to the output of the scan chain (if any one of the scan blocks has a tag bit with the no-pass value then the output of the final scan block in the scan chain will cause the input clock signal to be gated…Once the tag bits for all scan blocks for all scan block groups in the scan chain are the pass value, the output of the final scan block of the scan chain will generate an output signal causing gating circuit 516 to pass the input clock signal; Wang p. 0035)(The gating circuit may receive the output of the final scan block in the chain; Wang p. 0080).
Nguyen in view of Corso in further view of Wang, as combined, does not explicitly teach wherein the load detection flip- flop comprises a D flip-flop
a clock input coupled to an output of the clock supply circuit, and an output coupled to the input of the combinatorial logic.
However, Agashe in an analogous art teaches wherein the load detection flip- flop comprises a D flip-flop (a DQ flip-flop, having a clock input, a D-input and a Q-output, the clock input coupled to receive the test clock signal, the D-input coupled to receive the scan enable signal; Agashe Claim 3);
a clock input coupled to an output of the clock supply circuit, and an output coupled to the input of the combinatorial logic (DQ flip-flop 302 receives the scan enable signal SCAN.sub.EN and the test clock signal TEST.sub.CLK; Agashe p. 0046)(generate the clock signal CLK.sub.A for scan chain group A; Agashe p. 0043)(AND gate 420 connects to the output of flip-flop 416 and receives the test clock signal TEST; Agashe p. 0047)(a third AND gate coupled to the Q-output of the first DQ flip-flop and coupled to receive the test clock signal; Agashe Claim 4).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Nguyen in view of Corso in further view of Wang with the teachings of Agashe by configuring a D flip-flop, a clock input coupled to an output of the clock supply circuit, and an output coupled to the input of the combinatorial logic.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ D flip-flop in the system of Nguyen in view of Corso in further view of Wang because Agashe teaches signals are used for gating off the clock pulse whenever there is a transition on scan enable which is necessary as one clock pulse is needed for the transition on the scan enable input SCAN to be registered internally (Agashe p. 0046).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
NARAYANAN et al (US 20200309851 A1) teaches a first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.
Dev et al (US 8719651 B1) teaches an apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.
LIN (CN 101663648 A) teaches a low power consumption testing scheme, and can be various compression hardware structure are integrated together (e.g., an embedded deterministic test ("EDT") structure). In an embodiment of the present invention, an integrated circuit comprising a programmable testing stimulus selector, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuit. at the same time claims a testing vector generating method, these methods can be used to generate testing vector.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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