DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/17/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (Publication number: US 2021/0020109) in view of Jeong et al (Publication number: US 2021/0118374).
Consider Claim 1, Lin et al shows a display device (see figure 2), comprising:
(a) A display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines (see figures 2 and 7).
(b) Wherein the plurality of pixels include: a first transistor connected between a driving voltage line and a second node (see figure 3; and paragraphs 54-56); (The first transistor is read as Tdrive, and the second node is read as Node3).
(c) A sixth transistor connected between the second node and a common voltage line (see figure 3; and paragraphs 54-56); (The sixth transistor is read as Tem2).
(d) A light emitting element connected between the sixth transistor and the common voltage line (see figure 3; and paragraph 57); (Read as OLED 304, and the common voltage line is read as VSSEL).
(e) A fourth transistor connected between the second node and an initialization voltage line (see figure 3; the fourth transistor is read as Tini1).
(f) The gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels (see figure 4; and paragraphs 65-69); (see scanning signals scan1(n); scan2(n-1); and scan2(n)).
However, Lin et al does not specifically show delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels.
In the same field of endeavor, Jeong et al shows delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels (see paragraph 101); (The first scan signal of a logic low level, such as “Sro1”, is output from the first scan signal generation circuit SR[1], and after a predetermined time, delay a second scan signal of a logic low level, such as “Sro2”, is output from the second scan signal generation circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan signal delay of Jeong et al into the teaching of Lin et al in order to simplify circuit configuration (see Jeong et al; paragraphs 5-7).
Consider Claim 19, Lin et al shows an electronic device including a display device, the electronic device (see figure 2), comprising:
(a) A display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines (see figures 2 and 7).
(b) Wherein the plurality of pixels include: a first transistor connected between a driving voltage line and a second node (see figure 3; and paragraphs 54-56); (The first transistor is read as Tdrive, and the second node is read as Node3).
(c) A sixth transistor connected between the second node and a common voltage line (see figure 3; and paragraphs 54-56); (The sixth transistor is read as Tem2).
(d) A light emitting element connected between the sixth transistor and the common voltage line (see figure 3; and paragraph 57); (Read as OLED 304, and the common voltage line is read as VSSEL).
(e) A fourth transistor connected between the second node and an initialization voltage line (see figure 3; the fourth transistor is read as Tini1).
(f) The gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels (see figure 4; and paragraphs 65-69); (see scanning signals scan1(n); scan2(n-1); and scan2(n)).
However, Lin et al does not specifically show delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels.
In the same field of endeavor, Jeong et al shows delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels (see paragraph 101); (The first scan signal of a logic low level, such as “Sro1”, is output from the first scan signal generation circuit SR[1], and after a predetermined time, delay a second scan signal of a logic low level, such as “Sro2”, is output from the second scan signal generation circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan signal delay of Jeong et al into the teaching of Lin et al in order to simplify circuit configuration (see Jeong et al; paragraphs 5-7).
Claim 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (Publication number: US 2021/0020109) in view of Sun et al (Publication number: US 2024/0257732) in view of Jeong et al (Publication number: US 2021/0118374).
Consider Claim 2, Lin et al shows that the plurality of pixels further include:
(a) A second transistor connected between a data line and a first node (see figure 3); (The second transistor is read as Tdata).
(b) A third transistor connected between a third node and the second node (see figure 3); (The third transistor is read as Toxide).
(c) An eighth transistor connected between an anode electrode of the light emitting element and a light emitting initialization line (see figure 3); (The eighth transistor is read as Tini2).
(d) The first transistor is connected between the first node and the second node, and a gate electrode of the first transistor is connected to the third node (see Tdrive that is connected between Node3 (read second node, and Node1 (read as first node). Further the gate of Tdrive is connected to Node2 (read as third node).
However, Lin et al does not specifically show a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node.
In related art, Sun et al shows a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node (see figure 54 and paragraphs 433-436); (see T5 in figure 5 of Sun et al that is connected in a similar manner to T5 of the instant application. Further, T0 is read as the seventh transistor).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate T5 and T0 of Sun et al into the driving circuit of Lin et al in order to improve hysteresis problems (see Sun et al; paragraphs 433-436).
However, Lin et al, and Sun et al does not specifically show delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels.
In the same field of endeavor, Jeong et al shows delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels (see paragraph 101); (The first scan signal of a logic low level, such as “Sro1”, is output from the first scan signal generation circuit SR[1], and after a predetermined time, delay a second scan signal of a logic low level, such as “Sro2”, is output from the second scan signal generation circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan signal delay of Jeong et al into the teaching of Lin et al, and Sun et al in order to simplify circuit configuration (see Jeong et al; paragraphs 5-7).
Consider Claim 13, Lin et al shows a display device (see figure 2), comprising:
(a) A display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines (see figures 2 and 7).
(b) Wherein the gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels (see figure 4; and paragraphs 65-69); (see scanning signals scan1(n); scan2(n-1); and scan2(n)).
(c) The plurality of pixels include: a first transistor connected between a driving voltage line and a second node (see figure 3; and paragraphs 54-56); (The first transistor is read as Tdrive, and the second node is read as Node3).
(d) A second transistor connected between a data line and a first node (see figure 3); (The second transistor is read as Tdata).
(e) A third transistor connected between a third node and the second node (see figure 3); (The third transistor is read as Toxide).
(f) A fourth transistor connected between the second node and an initialization voltage line (see figure 3; the fourth transistor is read as Tini1).
(g) A sixth transistor connected between the second node and a common voltage line (see figure 3; and paragraphs 54-56); (The sixth transistor is read as Tem2).
(h) An eighth transistor connected between an anode electrode of a light emitting element and a light emitting initialization line (see figure 3); (The eighth transistor is read as Tini2).
(i) The light emitting element connected between the sixth transistor and the common voltage line (see Tdrive that is connected between Node3 (read second node, and Node1 (read as first node). Further the gate of Tdrive is connected to Node2 (read as third node).
However, Lin et al does not specifically show a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node.
In related art, Sun et al shows a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node (see figure 54 and paragraphs 433-436); (see T5 in figure 5 of Sun et al that is connected in a similar manner to T5 of the instant application. Further, T0 is read as the seventh transistor).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate T5 and T0 of Sun et al into the driving circuit of Lin et al in order to improve hysteresis problems (see Sun et al; paragraphs 433-436).
However, Lin et al, and Sun et al does not specifically show delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels.
In the same field of endeavor, Jeong et al shows delaying a phase of a second gate scan signal among the gate scan signals, the second gate scan signal being different from the first gate scan signal, and supplying the first gate scan signal and the second gate scan signal to the plurality of pixels (see paragraph 101); (The first scan signal of a logic low level, such as “Sro1”, is output from the first scan signal generation circuit SR[1], and after a predetermined time, delay a second scan signal of a logic low level, such as “Sro2”, is output from the second scan signal generation circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the scan signal delay of Jeong et al into the teaching of Lin et al, and Sun et al in order to simplify circuit configuration (see Jeong et al; paragraphs 5-7).
Allowable Subject Matter
Claims 3-12, 14-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 09/27/2026
