DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,334,872. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant seeks broader scope of previously patented claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa, US Pub. No. 2017/0263185, in view of Lee et al. (hereinafter “Lee”), US Pub. No. 2006/0290619.
Regarding claim 1, Nakagawa teaches a gamma voltage generation circuit ([0044-0046, figs. 3-4 which teach the gradation voltage generating circuit 60) comprising: a resistor string (fig. 4, resistors 63) a first operational amplifier circuit connected to an uppermost end of the resistor string and configured to output a first voltage corresponding to a highest voltage of the resistor string ([0046-0049, fig. 4 which teaches a plurality of “offset cancelling amplifier 64”, each one being connected between each resistor 63. The resistors 63 are connected in series and form thus de facto a resistor string. The first “offset-canceling amplifier 64”, of said plurality of “offset-canceling amplifier 64” constitutes a “first operational amplifier circuit”), a second operational amplifier circuit connected to a lowest end of the resistor string and configured to output a second voltage corresponding to a lowest voltage of the resistor string ([0046-0049 and fig. 4 which teaches a plurality of “offset-canceling amplifier 64”, each one being connected between each resistor 63. The resistors 63 are connected in series and form thus de facto a resistor string. The last “offset-canceling amplifier 64” of the plurality of “offset-canceling amplifier 64” constitutes “a second operational amplifier circuit.”) and a third operational amplifier circuit connected to a node of the resistor string configured to divide the first voltage and the second voltage to output a third voltage ([0046-0049, fig. 4, teaches a plurality of “offset-canceling amplifier 64”, each one being connected between each resistor 63. The resistors 63 are connected in series and form thus de factor a resistor string. Any one of the “offset-canceling amplifier 64” between the first and last of the “offset-canceling amplifier 64” constitutes a “third operational amplifier circuit”), wherein the third operational amplifier circuit includes a first offset elimination circuit configured to eliminate an offset voltage through charging and discharging of a capacitor ([0049, 0059-0060, figs. 4, 6B which teaches that the “offset-canceling amplifier 64” comprises an offset elimination circuit formed of the switches SW1-SW4 and capacitor 66. The offset voltage is charged across the capacitor 66.), and the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate an offset voltage ([0049, 0059-0060, fig. 4, 6B which teaches that each of the “offset-canceling amplifier 64” – including the first and last ones comprise an offset elimination circuit formed of the switches SW1-SW4 and capacitor 66).
Nakagawa fails to explicitly teach wherein the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate an offset voltage in a manner different from that of the third operational amplifier circuit by at least one of an Auto-Zeroing and a chopping method.
However, in the same field of endeavor, Lee teaches a gamma voltage generation circuit wherein the operational amplifier circuits are configured to eliminate an offset voltage by using the chopper method (see [0061-0063], figs. 4-5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify Nakagawa to include the feature of Lee. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to provide a device that applies the most efficient offset compensation technique.
Regarding claim 2, Nakagawa teaches wherein the first offset elimination circuit performs a sampling operation in a first time interval to charge an offset voltage of a first sub-operational amplifier circuit to a first capacitor and performs an offset elimination operation in a second time interval to eliminate the offset voltage of the first sub- operational amplifier circuit based on a voltage stored in the first capacitor ([0059-0060], figs. 6A-6B, teaches the operation of the “offset-canceling amplifier 64”).
Regarding claims 3 and 4, Nakagawa teaches wherein the first offset elimination circuit includes: a first sub-operational amplifier; a first switch electrically connected to a first input terminal of the first sub-operational amplifier a first capacitor electrically connected to a second input terminal of the first sub- operational amplifier and storing an offset voltage of the first sub-operational amplifier; a second switch electrically connected to the second input terminal and an output terminal of the first sub-operational amplifier and forming a common node with the first capacitor; a third switch electrically connected to the first switch and the first capacitor and forming a common node with the first switch and the first capacitor; and a fourth switch electrically connected to the output terminal of the first sub-operational amplifier ([0049,0060], fig. 4 teaches the offset canceling amplifier 64 comprising four switches SW1-SW4 and capacitor 66 having the claimed electrical connectivity and which are controlled such as to operate the offset cancelling amplifier according to a sampling period and offset compensation period.
Regarding claims 5-7, Examiner takes official notice that it would have been well known and obvious to a person having ordinary skill in the art to utilize an alternate operational amplifier circuit in place of the offset-cancelling amplifier in Nakagawa. It is common knowledge that a variation of the auto-zero method involves using two auto-zero amplifiers mounted in parallel wherein the operation between each amplifier is alternated. The prior art reference to Nakahira et al. (US Pub. No. 2006/0098032) is cited as illustration of the common general knowledge (see [0006-0009], fig. 46).
Regarding claims 8-10, Lee teaches wherein the amplifier 500 comprises chopping switches 520 and 530 which are operated so as to periodically exchange the inputs of the amplifier and alternatively connect the output to the amplifier to the inverted and non-inverted input. Implementation of the chopping method to compensate offset in the first and second operational amplifier circuits of Nakagawa would be obvious to a person having ordinary skill in the art according to design needs and specifications.
Regarding claim 11, it is a data driving circuit of claim 1 and is rejected on the same grounds presented above.
Regarding claim 12, it has similar limitations to those of claim 2 and is rejected on the same grounds presented above.
Regarding claim 13, it has similar limitations to those of claim 10 and is rejected on the same grounds presented above.
Regarding claim 14, it has similar limitations to those of claim 3 and is rejected on the same grounds presented above.
Regarding claim 15, it has similar limitations to those of claim 8 and is rejected on the same grounds presented above.
Regarding claim 17, it is a method of claim 1 and is rejected on the same grounds presented above.
Regarding claim 18, it has similar limitations to those of claim 5 and is rejected on the same grounds presented above.
Regarding claim 19, it has similar limitations to those of claim 3 and is rejected on the same grounds presented above.
Regarding claim 20, it has similar limitations to those of claim 9 and is rejected on the same grounds presented above.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa in view of Lee as applied to claim 1 above, and further in view of Lim et al. (hereinafter “Lim”), US Pub. No. 2022/0328012.
Regarding claim 16, Nakagawa and Lee fail to explicitly teach wherein, in the first operational amplifier circuit, an input terminal is connected to a first multiplexer supplied with a voltage, and an output signal supplied from an output terminal is not divided, and in the second operational amplifier circuit, an input terminal is connected to a second multiplexer supplied with a voltage, and an output signal supplied from an output terminal is not divided.
However, in the same field of endeavor, Lim teaches a gamma block wherein amplifier circuits are connected to multiplexers (see fig. 5A).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify Nakagawa and Lee to include the feature of Lim. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to reduce power consumption when generating gamma voltages (Lim, [0005]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ahmad et al. (US Pub. No. 2015/0236648) teaches a gamma voltage generation circuit including a first, second, and third operational amplifier.
Oh et al. (US Pub. No. 2023/0119029) teaches a gamma voltage generation circuit including a plurality of voltage dividing circuits using series-connected resistors and a plurality of multiplexers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B LEE JR whose telephone number is (571)270-3147. The examiner can normally be reached Mon - Fri 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached on 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625