Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Obviousness Type Double Patenting Rejection
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
2. Claims 1-10 and 16-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 and 3 of U.S. Patent No. 12327519 in view of Toyotaka (US 20200320930 A1).
See the comparison bellow:
Patent No: 12327519
1. A display pixel comprising:
a drive transistor having a drain terminal, a gate terminal, and a source terminal;
a light-emitting diode having an anode terminal coupled to the source terminal of the drive transistor;
a first capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the source terminal of the drive transistor;
3. The display pixel of claim 1, further comprising: a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a reference voltage line, and a gate terminal configured to receive a second scan signal different than the first scan signal.
Cont…of claim 1:
a second capacitor having a first terminal coupled to the source terminal of the drive transistor and having a second terminal coupled to a static voltage line; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal that is asserted during a data programming phase;
and a noise isolation transistor coupled in series with the second capacitor between the static voltage line and the source terminal of the drive transistor, wherein the noise isolation transistor is activated during the data programming phase.
1. A display pixel comprising:
a drive transistor having a drain terminal, a gate terminal, and a source terminal;
a light-emitting diode having an anode terminal coupled to the source terminal of the drive transistor;
a first capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the source terminal of the drive transistor;
3. The display pixel of claim 1, further comprising: a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a reference voltage line, and a gate terminal configured to receive a second scan signal different than the first scan signal.
Cont…of claim 1:
a second capacitor having a first terminal coupled to the source terminal of the drive transistor and having a second terminal coupled to a static voltage line; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal that is asserted during a data programming phase;
and a noise isolation transistor coupled in series with the second capacitor between the static voltage line and the source terminal of the drive transistor, wherein the noise isolation transistor is activated during the data programming phase.
Current Application 19210870
1. A display pixel comprising:
a light-emitting diode; a drive transistor coupled in series with the light-emitting diode;
a first capacitor having a first terminal coupled to a gate terminal of the drive transistor and having a second terminal coupled to a source terminal of the drive transistor;
a gate-voltage-setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor and having a second source-drain terminal configured to receive a reference voltage;
a second capacitor having a first terminal coupled to the source terminal of the drive transistor; and
a noise isolation transistor having a first source-drain terminal coupled to a second terminal of the second capacitor and having a second source-drain terminal configured to receive the reference voltage.
Claim 16. A display pixel comprising:
a light-emitting diode; a drive transistor configured to drive a current into the light-emitting diode;
a pass transistor configured to pass a reference voltage onto a gate terminal of the drive transistor;
a first capacitor coupled across the gate terminal and a source terminal of the drive transistor; and
a second capacitor having a first terminal coupled to the source terminal of the drive transistor and having a second terminal
configured to selectively receive the reference voltage.
Although the claims at issue patent are not identical, they are not patentably distinct from each other because except for minor wording and insignificant changes in terminology, each claim limitation of Patent 12327519 reads on the corresponding limitation of Application 19210870 except the limitations “a second capacitor having a first terminal coupled to the source terminal of the drive transistor and having a second terminal configured to selectively receive the reference voltage” as recited in claims 1 and 16.
However, Toyotaka (US 20200320930 A1) discloses a first capacitor (C2) having a first terminal coupled to a gate terminal of the drive transistor and having a second terminal coupled to a source terminal of the drive transistor ([0130-0132]], Fig. 6A); a gate-voltage-setting transistor (Tr2) having a first source-drain terminal coupled to the gate terminal of the drive transistor (Tr3) and having a second source-drain terminal configured to receive a reference voltage (WDL) ( Figs. 6A, 8; [0154]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patent 12327519 with the teaching of Toyotaka, thereby providing high-efficient data transmission in the display device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1, 2 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyotaka (US 20200320930 A1) in view of Lee et al (US 20200076411).
Regarding claim 1:
Toyotaka (US 20200320930 A1) discloses a display pixel (in Fig. 6A) comprising:
a light-emitting diode (LD) ([0130-0136]);
a drive transistor (Tr3) coupled in series with the light-emitting diode (LD) [0130-0136];
a first capacitor (C2) having a first terminal coupled to a gate terminal of the drive transistor and having a second terminal coupled to a source terminal of the drive transistor ([0130-0132]], Fig. 6A);
a gate-voltage-setting transistor (Tr2) having a first source-drain terminal coupled to the gate terminal of the drive transistor (Tr3) and having a second source-drain terminal configured to receive a reference voltage (WDL) ( Figs. 6A, 8; [0154]);
a second capacitor (C3) having a first terminal coupled to the source terminal of the drive transistor and ([0126-0130]).
Toyotaka discloses an isolation transistor (Tr7) coupled second capacitor (C3) having source-drain (([0126-0130]A, Fig. 6A).
Toyotaka does not specifically disclose noise from the power source.
Lee (US 20200076411) discloses noise from the power source (Vdd) and isolation transistor (570) coupled with a capacitor(440) (see Fig. 5 and [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Toyotaka with the teaching of Lee, thereby reduce luminance deviation among pixels.
Regarding claim 2:
Toyotaka discloses a data loading transistor (Tr1) having a first source-drain terminal coupled to the gate terminal of the drive transistor (Tr3) and having a second source-drain terminal coupled to a data line (DL) ([0004, 0112], Figs. 4, 6A, 14A1).
Regarding claim 11:
Toyotaka (US 20200320930 A1discloses a method of operating a display pixel having light-emitting diode (see Fig. 6A),
a drive transistor (Tr3) coupled in series with the light-emitting diode (LD), a first capacitor (C2) coupled across gate and source terminals of the drive transistor ([0130-0136]),
a pass transistor (Tr2) coupled to the gate terminal of the drive transistor (Tr3), and a second capacitor (C3) having a first terminal coupled to the source terminal of the drive transistor, the method comprising: during an emission phase, using the drive transistor to drive a current through the light- emitting diode ([0130-0136], Fig. 6A); during an initialization phase, using the pass transistor to pass a reference voltage onto the gate terminal of the drive transistor (voltage at WDL) ( Figs. 6A, 8; [0154]);
and during the initialization phase, activating a isolation transistor (Tr7) to pass the reference voltage onto a second terminal of the second capacitor (C3) [(([0126-0130]A, Fig. 6A).
Toyotaka does not specifically disclose noise from the power source.
Lee (US 20200076411) discloses noise from the power source (Vdd) and isolation transistor (570) coupled with a capacitor(440) (see Fig. 5 and [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Toyotaka with the teaching of Lee, thereby reduce luminance deviation among pixels.
4. Claim(s) 3-6, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyotaka (US 20200320930 A1, ID) in view of Lee et al (US 20200076411) further in view of Zheng (US 20210312864 A1).
Regarding claim 3:
Toyotaka in view of Lee does not specifically discloses display pixel further comprising: a first emission transistor having a first source-drain terminal coupled to drive transistor and having a second source-drain terminal coupled to a power supply line; and second emission transistor having a first source-drain terminal coupled to the drive transistor and having a second source-drain terminal coupled to an anode of the light-emitting diode.
Zheng discloses the display pixel, further comprising:
a first emission transistor (T3 for emission E1) having a first source-drain terminal coupled to drive transistor (T2) and having a second source-drain terminal coupled to a power supply line ((see Figs. 5-6) ([0039-0044]) ; and a second emission transistor (T4 for emission E2) having a first source-drain terminal coupled to the drive transistor and having a second source-drain terminal coupled to an anode of the light-emitting diode (see Figs. 5-6) ([0039-0044]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Toyotaka with the teaching of Lee and Zheng, thereby providing uniform lumination in the display device.
Regarding claim 4:
Toyokata discloses a reset transistor (reset by Tr5) having a first source-drain terminal coupled to the anode of the light- emitting diode and having a second source-drain terminal configured to receive a reset voltage (voltage rest by Tr5) that is separate from the reference voltage (WDL) (see Fig. 8-9, [0151-0152]).
Regarding claim 5:
Toyokata in view of Lee and Zheng discloses wherein the first emission transistor (T3) and the reset transistor (Tr5) are configured to receive a first emission signal (signal on E1) (see Zheng Figs.6A, 8, [0150, 0177]). Same motivation as recited in claim 3.
Regarding claim 6:
Toyokata in view of Lee and Zheng discloses discloses wherein the second emission transistor (T4) is configured to receive a second emission signal different than the first emission signal (see Zheng Figs. 5-6) ([0039-0044]). Same motivation as recited in claim 3.
Regarding claim 12:
Toyotaka in view of Lee discloses wherein the noise isolation transistor is deactivated during the emission phase (see Toyotaka [0130-0136], Lee (see Fig. 5 and [0039]). Same motivation as applied to claim 11.
5. Claim(s) 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyotaka (US 20200320930 A1, ID) in view of Guo (US 20130120337).
Regarding claim 16:
Toyotaka (US 20200320930 A1) discloses a display pixel (in Fig. 6A) comprising:
a light-emitting diode (LD) ([0130-0136]);
a drive transistor (Tr3) configured to drive a current into the light-emitting diode (LD) [0130-0132];
a pass transistor (Tr2) configured to pass a reference voltage (potential V.sub.1 to the wiring WDL, see [0199-0200]) onto a gate terminal of the drive transistor (Tr3) (also see Figs. 6A, 8; [0154]);
; a first capacitor (C2) coupled across the gate terminal and a source terminal of the drive transistor [Tr3]; and
a second capacitor (C2) having a first terminal coupled to the source terminal of the drive transistor and having a second terminal configured to selectively receive the reference voltage (i.e. potential V.sub.1through the Tr2, see).
Toyotaka disclose a second capacitor (C3, see Fig. 6A). However, Toyokata does not specifically disclose a second capacitor having a first terminal coupled to the source terminal of the drive transistor and having a second terminal configured to selectively receive the reference voltage.
However, Guo (US 20130120337) discloses a second capacitor (234) having a first terminal coupled to the source terminal of the drive transistor (21) and having a second terminal configured to selectively receive the reference voltage (Ref) (see Fig. 2, [0023-0024].
Regarding claim 19:
Toyokata discloses wherein the second terminal of the second capacitor (C3 connected to the Tr3 through the Node ND4) is not directly coupled to the drive transistor.
6. Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyotaka (US 20200320930 A1, ID) in view of Guo and further in view of Lee et al (US 20200076411).
Regarding claim 17:
Toyotaka discloses an isolation switch (Tr7) coupled second capacitor (C3) having source-drain (([0126-0130]A, Fig. 6A) configured to receive the reference voltage (voltage at WDL) ( Figs. 6A, 8; [0154]);
Toyotaka does not specifically disclose noise from the power source.
Lee (US 20200076411) discloses noise from the power source (Vdd) and isolation transistor (570) coupled with a capacitor(440) (see Fig. 5 and [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Toyotaka with the teaching of Lee, thereby reduce luminance deviation among pixels.
Regarding claim 18:
Toyokata in view of Guo and Lee discloses wherein the noise isolation switch (Tr7, see Toyokata Fig. 6A) is not directly coupled (Tr7 coupled through the node ND4) to the drive transistor (Tr3) (also see Lee Fig. 5, [0039]) sale motivation as applied to claim 17.
Allowable subject matter
7. Claims 7-10, 13-15, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if overcome the TD and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7:
The closest art of record singly or in combination fails to teach or suggest the limitations “the data loading transistor (Tdata) is configured to receive a first scan signal (Scann1); the gate-voltage-setting transistor (Tref) is configured to receive a second scan signal different than the first scan signal (see Fig. 5A, [0049]); and the noise isolation transistor (Tiso) is configured to receive a third scan signal different than the first and second scan signals (see Applicant’s disclosure [0049-0052], Fig. 5A)” as recited in claim 7.
Regarding claim 13:
The closest art of record singly or in combination fails to teach or suggest the limitations “first and second emission transistors (Tm1, Tm2) coupled in series with the drive transistor and the light-emitting diode, during a threshold voltage sampling phase, activating the pass transistor, the first emission transistor, and the noise isolation transistor (see Applicant’s disclosure [0049-0052], Fig. 5A)” as recited in claims13.
Regarding claim 20:
The closest art of record singly or in combination fails to teach the limitations “a first emission transistor (Tm1) coupled between the drive transistor (Tdrive) and a positive power supply line (VDDEL); a second emission transistor (Tm2) coupled between the drive transistor and the light-emitting diode (26) with all other limitations as recited in claim 20” (see applicant’s disclosure, Fig. 5A, [0072]).
Pertinent Art
8. Pertinent art of record US 20090091561 A1discloses display device.
Inquiry
9. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Shaheda Abdin whose telephone number is (571) 270-1673.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao could be reached at (571) 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHEDA A ABDIN/ Primary Examiner, Art Unit 2621