DETAILED ACTION
Reissue
The present reissue application is directed to US 11,652,062 B2 (“062 Patent”). 062 Patent issued on May 16, 2023 with claims 1-9 from application 16/706,563 filed on December 9, 2019, which is a continuation of parent application 16/279,814 filed on February 19, 2019 (now US 10,504,848 B2).
This application was filed on May 16, 2025. Since this date is after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Furthermore, the present application is being examined under the first inventor to file provisions of the AIA .
This application presents broadened claims, which are permitted because Applicant filed these claims and demonstrated an intent to broaden within two years of the issue date of 062 Patent.
The most recent amendment was filed on October 21, 2025. The status of the claims is:
Claims 1-9: Original
Claims 10-30: New
This is a first, non-final action.
References and Documents Cited in this Action
062 Patent (US 11,652,062 B2)
Sturcken (US 2020/0075541 A1)
Li (US 2017/0064837 A1)
Summary of Rejections and Objections in this Action
Claims 12 and 23-30 are rejected under 35 U.S.C. 112(b) as being indefinite.
Claims 10 and 13-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sturcken.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sturcken in view of Li.
Claims 1-9 are allowed.
Summary of the Claims
062 Patent is directed to a voltage regulator configured to provide power to a chip. Claim 10 is representative:
10. An electronic device comprising:
a package having a first side and a second side opposite the first side;
a semiconductor die mounted onto the first side of the package; and
a plurality of chip-embedded power converters that are coupled in parallel and mounted onto the second side of the package, wherein the plurality of chip-embedded power converters are coupled through the package to the semiconductor die and are configured to deliver power to the semiconductor die.
Claims 1, 10, and 23 are the independent claims. Claim 1 further recites other elements including an additional power converter, an interposer, power switches, and an inductor. Claim 23 further recites a package substrate.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 23-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “the chip-embedded power converters can have circuitry that is embedded in a printed circuit board.” The claim is indefinite because it is unclear whether circuitry that is embedded in a printed circuit board is necessarily part of the claimed electronic device.
Claim 23 recites “a plurality of chip-embedded power converters that separate from the semiconductor die.” The claim is indefinite because it is unclear whether the claimed device includes power converters that would somehow separate (i.e., detach) from the semiconductor die or rather, are separate (i.e., are distinct) from the semiconductor die. Based on the specification of 062 Patent, Examiner suggests Applicant amend the limitation to recite “are separate.” Claims 24-30 depend on claim 23 and are indefinite for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10 and 13-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sturcken.
Regarding independent claim 10, Sturcken discloses an electronic device (Figures 2A and 3) comprising:
a package 210 having a first side 212 and a second side 214 opposite the first side;
a semiconductor die 200 mounted onto the first side of the package; and
a plurality of chip-embedded power converters 230 that are coupled in parallel and mounted onto the second side of the package, wherein the plurality of chip-embedded power converters are coupled through the package to the semiconductor die and are configured to deliver power to the semiconductor die (paragraphs [0031]-[0037] and [0042]).
Regarding claim 13, Sturcken discloses that each of the plurality of power converters (Figure 6) comprises:
a plurality of chip-embedded power switches (i.e., transistor gates 662 and 664; paragraphs [0052]-[0054]); and
an inductor 670 coupled to the plurality of power switches (paragraphs [0052]-[0054]).
Regarding claim 14, Sturcken discloses that a footprint of the inductor at least partially overlaps a footprint of the chip-embedded power switches (e.g., Figure 7 shows a footprint of inductor 770 partially overlapping switches 662 and 664; paragraphs [0060]-[0066]).
Regarding claim 15, Sturcken discloses that the plurality of power converters comprise chip embedded circuitry that includes a pulse width modulator (PWM) controller (i.e., feedback control circuitry 620; Figure 6) configured to generate one or more PWM signals and a driver (i.e., regulation circuitry 640) configured to generate one or more driver signals based at least in part on the one or more PWM signals, wherein the plurality of chip-embedded power switches are driven by the one or more driver signals (paragraphs [0055]-[0058]).
Regarding claim 16, Sturcken discloses that the semiconductor die 200 comprises a computer processor (Figure 2A; paragraph [0031]).
Regarding claim 17, Sturcken discloses that the plurality of power converters 230 are configured to receive electrical power having a first voltage VIN and to modify the electrical power to provide electrical power having a second voltage VDD lower than the first voltage VIN, and wherein the semiconductor die 200 is configured to use the second voltage VDD (paragraph [0042]; Figure 3).
Regarding claim 18, Sturcken discloses that the second voltage is about 0.4 V to about 1 V (i.e., “In one example,…the supply voltage VDD is about 0.8 V”; paragraph [0042]; Figure 3).
Regarding claim 19, Sturcken discloses that the second voltage is about 1 V to about 4 V (i.e., “In some embodiments, the supply voltage VDD is about 1.8 V, 1.2 V, 1.2 V-0.4 V”; paragraph [0042]; Figure 3).
Regarding claim 20, Sturcken discloses that the plurality of chip-embedded power converters 230 are coupled to the semiconductor die 200 by vias 218 (i.e., conductive columns 218 in Figure 2A; paragraphs [0037]; Sturcken discloses that columns 218 are also known as vias; paragraph [0079]).
Regarding claim 21, Sturcken discloses contacts (i.e., terminals 215) that provide input and/or output connections for the semiconductor die, and wherein the plurality of chip-embedded power converters 230 are positioned between the contacts (Figure 2A; paragraph [0034]-[0036]).
Regarding claim 22, Sturcken discloses that the plurality of chip-embedded power converters 230 are positioned within a footprint of the semiconductor die 200 (Figure 2A).
Regarding independent claim 23, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Sturcken discloses an electronic device (Figures 2A and 3) comprising:
a package substrate 210;
a semiconductor die 200 mounted onto the package substrate;
a plurality of chip-embedded power converters 230 that are separate from the semiconductor die, wherein the plurality of chip-embedded power converters 230 are coupled in parallel and mounted onto the package substrate, wherein the plurality of chip-embedded power converters are positioned within a footprint of the semiconductor die, wherein the plurality of chip-embedded power converters are coupled to the semiconductor die and are configured to deliver power to the semiconductor die (paragraphs [0031]-[0037] and [0042]).
Regarding claim 24, Sturcken discloses contacts (i.e., terminals 215) that provide input and/or output connections for the semiconductor die, and wherein the plurality of chip-embedded power converters 230 are positioned between the contacts (Figure 2A; paragraphs [0034]-[0036]).
Regarding claim 25, Sturcken discloses that the plurality of chip-embedded power converters 230 are surrounded by the contacts 215 (Figure 2A; paragraph [0034]-[0036]).
Regarding claim 26, Sturcken discloses that the plurality of chip-embedded power converters 230 are arranged as a grid or strip (e.g., Figure 2A shows at least a “strip” of several power converters 230).
Regarding claim 27, Sturcken discloses that the plurality of chip-embedded power converters 230 are configured to receive electrical power having a first voltage VIN and to modify the electrical power to provide electrical power having a second voltage VDD lower than the first voltage VIN, and wherein the semiconductor die 200 is configured to use the second voltage VDD (paragraph [0042]; Figure 3).
Regarding claim 28, Sturcken discloses that the package substrate 210 includes a front side 212 and a back side 214, wherein the semiconductor die 200 is mounted onto the front side of the package substrate, and wherein the plurality of chip-embedded power converters 230 are mounted onto the back side of the package substrate (Figure 2A; paragraphs [0031]-[0033]).
Regarding claim 29, Sturcken discloses that each of the plurality of chip-embedded power converters (Figure 6) comprises:
chip-embedded circuity comprising a plurality of power switches (i.e., transistor gates 662 and 664; paragraphs [0052]-[0054]); and
an inductor 670 coupled to the plurality of power switches (paragraphs [0052]-[0054]), wherein a footprint of the inductor at least partially overlaps a footprint of the chip-embedded circuitry (e.g., Figure 7 shows a footprint of inductor 770 partially overlapping switches 662 and 664; paragraphs [0060]-[0066]).
Regarding claim 30, Sturcken discloses that the chip embedded circuitry includes a pulse width modulator (PWM) controller (i.e., feedback control circuitry 620; Figure 6) configured to generate one or more PWM signals and a driver (i.e., regulation circuitry 640) configured to generate one or more driver signals based at least in part on the one or more PWM signals, wherein the plurality of power switches are driven by the one or more driver signals (paragraphs [0055]-[0058]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sturcken in view of Li.
Regarding claims 11 and 12, Sturcken discloses an electronic device as discussed above with regard to claim 10 including a package and chip-embedded power converters but does not specifically disclose an interposer of the package. However, Li teaches a device that is related to the one disclosed by Sturcken including a die 210, package substrate 212, and power converters (i.e., voltage regulators) 220, 222, and 224 (Li, Figure 2; paragraphs [0034]-[0036]). Regarding claim 11 in particular, Li further teaches that power converters 220, 222, and 224 have circuitry that is embedded in an interposer 202 of the package (paragraphs [0034]-[0036]). Regarding claim 12 in particular (as well as the claim may be understood with respect to 35 U.S.C> 112(b) as discussed above), Li further teaches that power converters 220, 222, and 224 can have circuitry that is embedded in a printed circuit board (PCB) 204, and wherein the PCB 204 is mounted onto an interposer 202 of the package (paragraphs [0034]-[0036]). Regarding claims 11 and 12, it would have been obvious to a person of ordinary skill in the art to include an interposer as taught by Li in the electronic device disclosed by Sturcken in order to advantageously reduce the overall footprint of the device and provide heat dissipation (Li, paragraph [0038]).
Allowable Subject Matter
Claims 1-9 are allowed.
The prior art does not specifically disclose or fairly suggest an electronic device including the combination of all of the elements, steps, and limitations recited in claims 1-9 (including all of the limitations of any respective parent claims), particularly including:
a processor package configured to receive the electrical power having the second voltage lower than a first voltage from the power converter, the processor package comprising a plurality of chip-embedded voltage regulators on the interposer, wherein the plurality of chip-embedded voltage regulators are coupled in parallel and are electrically coupled to the computer processor through the interposer, and wherein each of the plurality of chip-embedded voltage regulators comprises chip-embedded circuitry including a plurality of power switches configured to modify electrical power; and an inductor coupled to the chip-embedded circuitry, wherein a footprint of the inductor at least partially overlaps a footprint of the chip-embedded circuitry; wherein the plurality of chip-embedded voltage regulators on the interposer are configured to modify the electrical power received by the processor package to provide electrical power having a third voltage lower than the second voltage.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which this reissue application is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice.
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Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to Examiner Christina Leung at telephone number (571) 272-3023; the Examiner’s supervisor, SPE Patricia Engle at (571) 272-6660; or the Central Reexamination Unit at (571) 272-7705.
/CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991
Conferees:
/DEANDRA M HUGHES/Reexamination Specialist, Art Unit 3992
/Patricia L Engle/SPRS, Art Unit 3991
Prosecution Insights