DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office Action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Information Disclosure Statement (IDS)
No IDS has been filed for this application. Applicant is reminded of the duty to
disclose from section 2100 of the MPEP:
37 C.F.R. 1.56; Duty to disclose information material to patentability.
A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section.
Election/Restrictions
Applicant's election without traverse of Species II: Figure 6 in the reply filed on 04/20/2026 is acknowledged.
Claim Objections
Claim 1 is objected to because of the following informalities:
In Claim 1, “display device comprising: a display panel includes a display area and a non-display area; a data driving circuit disposed at least one side of the display area” should read “display device comprising: a display panel that includes a display area and a non-display area; a data driving circuit disposed at one side of the display area”.
In Claim 1, second data link line group disposed in the first areas” should read “second data link line group disposed in the first area”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent 12,334,023 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
The following is an example for comparing claim 1 of this application and claims 1 and 9-11 of U.S. Patent 12,334,023 B2:
Claim 1 of this application
Claims 1 and 9-11 of U.S. Patent 12,334,023 B2
1. A display device comprising:
a display panel that includes a display area and a non-display area;
a data driving circuit disposed at one side of the display area;
a plurality of data lines extending in a first direction in the display panel;
a plurality of driving voltage lines extending in the first direction in the display panel;
a plurality of gate lines extending in a second direction crossing to the first direction in the display panel;
a plurality of subpixels disposed in the display area, each having a driving transistor and a switching transistor; and
a plurality of data link lines extending from a data pad part connected to the data driving circuit in a direction of the display panel,
wherein the plurality of data lines comprising a first data line group disposed in a first area corresponding to the data driving circuit and a second data line group disposed in a second area outside of the data driving circuit,
wherein the plurality of data link lines comprising a first data link line group disposed in a data link area between the data pad part and the display panel and a second data link line group disposed in the first area and the second area,
wherein the first data link line group is electrically connected to the first data line group and
wherein the second data link line group is electrically connected to the second data line group.
1. A display device comprising:
a display panel comprising a plurality of data lines and a plurality of gate lines;
a data driving circuit supplying a data voltage to the plurality of data lines;
wherein the display panel includes a display area; wherein the display area includes a first area corresponding to the data driving circuit and a second area located outside the first area; a first data link line group having a linear structure and connected to a first data line group disposed in the first area among the plurality of data lines; and a second data link line group having a bending structure and connected to a second data line group disposed in the second areas among the plurality of data lines, wherein a bending point of the bending structure is located within the first area, and wherein the second data link line group having the bending structure comprises: (2-1)th data link lines extending from the data driving circuit to the first area; (2-2)th data link lines disposed in the first area and connected to the (2-1)th data link lines; and (2-3)th data link lines connecting the (2-2)th data link lines and the second data line group.
9. The display device according to claim 1, wherein the display panel further comprises a plurality of subpixels provided at intersections of the plurality of data lines and the plurality of gate lines, and
wherein each of the subpixels comprises:
a light-emitting element; and a driving transistor supplying driving current to the light-emitting element, wherein each of the (2-2)th data link lines is disposed to spaced away from the driving transistor or a source electrode of the driving transistor.
10. The display device according to claim 9, wherein each of the subpixels further comprises: a first switching transistor having a gate electrode to which a first scan signal is applied, a drain electrode connected to a gate electrode of the driving transistor, and a source electrode connected to a drain electrode of the driving transistor; a second switching transistor having a gate electrode to which a second scan signal is applied, a source electrode to which a data voltage is applied, and a drain electrode connected to the source electrode of the driving transistor; a third switching transistor having a gate electrode to which an emission signal is applied, a source electrode to which a high-potential driving voltage is applied through a driving voltage line, and a drain electrode connected to the source electrode of the driving transistor; a fourth switching transistor having a gate electrode to which the emission signal is applied, a source electrode connected to the drain electrode of the driving transistor, and a drain electrode connected to an anode of the light-emitting element; a fifth switching transistor having a gate electrode to which a fourth scan signal is applied, a drain electrode to which a stabilization voltage is supplied, and a source electrode connected to the gate electrode of the driving transistor and a storage capacitor;
a sixth switching transistor having a gate electrode to which a third scan signal is applied, a source electrode to which a reset voltage is supplied, and a drain electrode connected to the anode of the light-emitting element; and a seventh switching transistor having a gate electrode to which a fifth scan signal is applied, a source electrode to which a bias voltage is supplied, and a drain electrode connected to the source electrode of the driving transistor.
11. The display device according to claim 9, wherein each of the (2-2)th data link lines is disposed between the source electrode of the driving transistor and a driving voltage line, and disposed to be closer to the driving voltage line rather than the source electrode of the driving transistor.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1 and 9-11 of U.S. Patent 12,334,023 B2, either singularly or in combination, contains each and every element and/or render each and every element of claim 1 of the instant application obvious. The claims of the instant application therefore are not patently distinct from the issued patent claims and as such are unpatentable over obvious-type double patenting.
More specifically, the subject matter in claims 1 and 9-11 of U.S. Patent Number 12,334,023 discloses all the elements of independent claim 1 of the instant application except the features of a data pad part connected to the data driving circuit in a direction of the display panel. However, it would be obvious to a person of ordinary skill in the art at the time when the invention was filed to include a plurality of data link lines extending from a data pad part connected to a data driving circuit in a direction of the display panel in order to supply a data voltage to the data lines in a display device.
Claims 2-20 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent 12,334,023 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 12-13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2016/0307528 A1 to Zou et al. (hereinafter "Zou") in view of U.S. Patent Application Publication 2017/0154579 A1 to Choi et al. (hereinafter "Choi").
Regarding Claim 1, Zou teaches a display device comprising: a display panel that includes a display area and a non-display area (Abstract; Claims 1, 14; Figs. 4-5; Para. 49-69 of Zou; array layer includes a display region and a non-display region); a data driving circuit disposed at one side of the display area; a plurality of data lines extending in a first direction in the display panel; a plurality of gate lines extending in a second direction crossing to the first direction in the display panel (Abstract; Claims 1, 14; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… and a plurality of gate lines… which are arranged on the flexible substrate 100 in a crisscross manner so as to define a plurality of subpixel regions… data line 20… driving module 120 configured to output driving signals to the gate lines and the data lines… bendable display region and an unbendable non-display region, and the driving module 120 is arranged at the non-display region); a plurality of subpixels disposed in the display area, each having a switching transistor (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… and a plurality of gate lines… which are arranged on the flexible substrate 100 in a crisscross manner so as to define a plurality of subpixel regions… TFT 30 arranged at each subpixel region and connected to the corresponding data line 10 and gate line 20); and a plurality of data link lines connected to the data driving circuit in a direction of the display panel (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… and a plurality of gate lines… which are arranged on the flexible substrate 100 in a crisscross manner so as to define a plurality of subpixel regions… data line 20… driving module 120 configured to output driving signals to the gate lines and the data lines NOTE – lines connecting data lines 20 to driving module 120), wherein the plurality of data lines comprising a first data line group disposed in a first area corresponding to the data driving circuit (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… data line 20 is formed as a straight line NOTE – area corresponding to two middle data lines 20 on the left side of the bendable display region in Fig. 5) and a second data line group disposed in a second area outside of the data driving circuit (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… data line 20 is formed as a straight line NOTE – area corresponding to two leftmost data lines in the area to the left of the bendable display region in Fig. 5), wherein the plurality of data link lines comprising a first data link line group disposed in a data link area (Abstract; Claim 1; Figs. 4-5; Para. 49-68 of Zou; signal transmission lines including a plurality of data lines… and a plurality of gate lines… which are arranged on the flexible substrate 100 in a crisscross manner so as to define a plurality of subpixel regions… data line 20… driving module 120 NOTE – lines connecting two middle data lines 20 on the left side of the bendable display region in Fig. 5) and a second data link line group disposed in the first area and the second area, wherein the first data link line group is electrically connected to the first data line group and wherein the second data link line group is electrically connected to the second data line group (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… data line 20 is formed as a straight line NOTE – area corresponding to two leftmost data lines in the area to the left of the bendable display region in Fig. 5).
Zou does not explicitly disclose a plurality of driving voltage lines extending in the first direction in the display panel; subpixels having a driving transistor and a switching transistor; data link lines extending from a data pad part; a data link area between the data pad part and the display panel.
However, Choi teaches a plurality of driving voltage lines extending in a first direction in a display panel (Fig. 6; Para. 136-146 of Choi; driving voltage lines DVL1, DVL2); subpixels having a driving transistor and a switching transistor (Fig. 2; Para. 63 of Choi; each subpixel may basically include an OLED, a driving transistor DRT driving the OLED, a switching transistor SWT supplying a data voltage); data link lines extending from a data pad part (Abstract; Claim 1; Figs. 4-8; Para. 159-165 of Choi; pads DV1, DAT1, DAT2, RV1, DAT3, DAT4, DV2, DAT5, DAT6, RV2, DAT7, and DAT8 positioned on the pad region 800 of the non-active area N/A may be arranged in correspondence with an array of signal lines DVL1, DL1, DL2, RVL1, DL3, DL4, DVL2, DL5, DL6, RVL2, DL7, and DL8 in the active area A/A NOTE – lines connecting data lines DL1, DL2 to DAT1, DAT2); a data link area between the data pad part and the display panel (Abstract; Claim 1; Figs. 4-8; Para. 159-165 of Choi; pads DV1, DAT1, DAT2, RV1, DAT3, DAT4, DV2, DAT5, DAT6, RV2, DAT7, and DAT8 positioned on the pad region 800 of the non-active area N/A may be arranged in correspondence with an array of signal lines DVL1, DL1, DL2, RVL1, DL3, DL4, DVL2, DL5, DL6, RVL2, DL7, and DL8 in the active area A/A NOTE – lines connecting data lines DL1, DL2 to DAT1, DAT2 NOTE – area between pad region 800 and active area A/A).
Therefore, at the time when the invention was filed, it would have been obvious to a person of ordinary skill in the art to include a plurality of driving voltage lines extending in the first direction in the display panel; subpixels having a driving transistor and a switching transistor; data link lines extending from a data pad part; a data link area between the data pad part and the display panel using the teachings of Choi in order to modify the display device taught by Zou. The motivation to combine these analogous arts would have been to provide an organic light-emitting display device having a switching structure in which a common voltage pad able to be connected to a plurality of voltage lines without providing individual pads for each of the respective voltage lines, thereby reducing the number of pads to reduce a possibility of a short circuit occurring between the pads, and enabling accurate voltage transfer to the plurality of voltage lines (Para. 262 of Choi).
Regarding Claim 7, the combination of Zou and Choi teaches that the second data line group are disposed in the second area (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… data line 20 is formed as a straight line NOTE – area corresponding to two leftmost data lines in the area to the left of the bendable display region in Fig. 5) and are symmetric with respect to the first area (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… data line 20 is formed as a straight line NOTE – area corresponding to two middle data lines 20 on the left side of the bendable display region in Fig. 5).
Regarding Claim 12, the combination of Zou and Choi teaches that a width of a data pad part in which a first to a nth data pads are arranged horizontally, corresponds to a width of the data driving circuit (Abstract; Claim 1; Figs. 4-8; Para. 159-165 of Choi; non-active area N/A includes a pad region to which a source driver IC SDIC mounted film FL is bonded… non-active area N/A is provided with a pad region 800 on which pads DV1, DAT1, DAT2, RV1, DAT3, DAT4, DV2, DAT5, DAT6, RV2, DAT7, and DAT8 bonded with film pads).
Regarding Claim 13, the combination of Zou and Choi teaches that a width of the data driving circuit is smaller than a width of the display area, and a width of the data pad part is smaller than the width of the display area (Abstract; Claim 1; Figs. 4-8; Para. 159-165 of Choi; non-active area N/A includes a pad region to which a source driver IC SDIC mounted film FL is bonded… non-active area N/A is provided with a pad region 800 on which pads DV1, DAT1, DAT2, RV1, DAT3, DAT4, DV2, DAT5, DAT6, RV2, DAT7, and DAT8 bonded with film pads).
Regarding Claim 18, the combination of Zou and Choi teaches that the first data link line group having a linear structure and connected to the first data line group (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… and a plurality of gate lines… which are arranged on the flexible substrate 100 in a crisscross manner so as to define a plurality of subpixel regions… data line 20… driving module 120… NOTE – lines connecting two middle data lines 20 on the left side of the bendable display region in Fig. 5); and wherein the second data link line group having a bending structure and connected to the second data line group (Abstract; Claim 1; Figs. 4-5; Para. 49-69 of Zou; signal transmission lines including a plurality of data lines… and a plurality of gate lines… which are arranged on the flexible substrate 100 in a crisscross manner so as to define a plurality of subpixel regions… data line 20… driving module 120… NOTE – lines connecting data lines at the top left of the bendable display region in Fig. 5)
Claim 19 is rejected are under 35 U.S.C. 103 as being unpatentable over Zou in view of Choi, as applied to claim 1 above, and further in view of U.S. Patent Application Publication 2018/0122302 A1 to Koong (hereinafter "Koong").
Regarding Claim 19, the combination of Zou and Choi does not explicitly disclose dummy data link lines disposed to alternate with the plurality of the data lines of the second data line group of the second areas.
However, Koong teaches dummy data link lines disposed with data lines (Figs. 2-4; Para. 41-63 of Koong; data lines DL1 to DLd, and the dummy data lines DDL1 and DDL2).
Therefore, at the time when the invention was filed, it would have been obvious to a person of ordinary skill in the art to include dummy data link lines disposed to alternate with the plurality of the data lines of the second data line group of the second areas using the teachings of Koong in order to modify the device taught by the combination of Zou and Choi. The motivation to combine these analogous arts would have been to provide light sources and luminaires for preventing deterioration in bending portions of a bendable display panel (Para. 2 of Koong).
Potentially Allowable Subject Matter
Claims 2-6, 8-11, 14-17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims once the double patenting rejection referenced above is resolved. As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABHISHEK SARMA whose telephone number is (571)272-9887. The examiner can normally be reached on Mon - Fri 8:00-5:00.
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/ABHISHEK SARMA/
Primary Examiner, Art Unit 2621
Prosecution Insights