DETAILED ACTION
This office action is in response to application 19/211,690 filed 5/19/2025 that claims priority to provisional application 63/657,185 filed 6/7/2024.
Claims 1-20 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 3-7, 10-12, and 15-19 are objected to as being dependent upon a rejected base claims 1 and 13, but would be allowable if they were rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art does not teach or suggest ‘wherein the host command specifies the first tag and the second tag’.
The closest prior art is Gutierrez US 2024/0095184 A1 that teaches combining two in-flight address translations. However Gutierrez does not specify a single command with both a first and second tag, where a tag contains an address translation.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 4, the prior art does not teach or suggest ‘wherein the host command is received from a second host system, and wherein the host command specifies the second host system‘ within the context of claim 1.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 5, claim 5 depends from claim 4, and thus is objected to as dependent from a rejected base claim but would allowable based on its dependence from claim 4 above if it was rewritten in independent form including all of the limitations of the base claim and intervening claims 4.
Regarding claim 6, the prior art does not teach or suggest ‘wherein a capacity of the first memory section allocated to the first host system and associated with the first flag is immutable, and wherein a capacity of the second memory section allocated to the first host system and associated with the second flag is immutable‘ within the context of claim 1.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 7, the prior art does not teach or suggest ‘wherein the host command specifies at least one of: a region, of the plurality of dynamic capacity devices, for the third memory section, or a selection policy for selecting the third memory section’ within the context of claim 1 from which claim 7 depends.
This claim requires that the third memory section is identified in the host command.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 10, the prior art does not teach or suggest ‘creating the first tag responsive to receiving the first allocation request by a first node in an orchestrator cluster, …; and creating the second tag responsive to receiving the second allocation request by a second node in the orchestrator cluster, wherein the second node runs on the first host system’ within the context of claim 9 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 11, the prior art does not teach or suggest ‘wherein the processing device is to perform operations further comprising: deleting mapping of the first tag, the first memory section, and an identifier of the first host system; and deleting mapping of the second tag, the second memory section, and the identifier of the first host system’ within the context of claim 1 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 12, the prior art does not teach or suggest ‘wherein the first data and the second data are combined according to an order provided in the host command’ within the context of claim 1 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 15, similar to claim 3, the prior art does not teach or suggest ‘wherein the host command specifies the first tag and the second tag’.
The closest prior art is Gutierrez US 2024/0095184 A1 that teaches combining two in-flight address translations. However Gutierrez does not specify a single command with both a first and second tag (address translation).
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 16, similar to claim 4, the prior art does not teach or suggest ‘wherein the host command is received from a second host system, and wherein the host command specifies the second host system‘ within the context of claim 13 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 17, similar to claim 6, the prior art does not teach or suggest ‘wherein a capacity of the first memory section allocated to the first host system and associated with the first flag is immutable, and wherein a capacity of the second memory section allocated to the first host system and associated with the second flag is immutable’ within the context of claim 13 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 18, similar to claim 7, the prior art does not teach or suggest ’wherein the host command specifies at least one of: a region, of the plurality of dynamic capacity devices, for the second memory section, or a selection policy for selecting the second memory section’ within the context of claim 13 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Regarding claim 19, similar to claim 12, the prior art does not teach or suggest ‘wherein the first data and the second data are combined according to an order provided in the host command’ within the context of claim 13 from which it depends.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 9, 13, and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C 1-2 (a)(2) as being anticipated by Han (Han et al., US 2018/0300254 A1).
Regarding claim 1, Han teaches A system (Han [0068] discloses the inventive concepts might be implemented on a system on a chip) comprising: a memory device (Han Fig. 1 that shows environment 100 that is an example of a system that includes Non-volatile Storge Device 110.) comprising a plurality of dynamic capacity devices; (Han [0003] discloses the solution is directed to on-demand allocation where a total logical capacity is larger than the physical capacity. Han [0025] discloses data may be stored on a non-volatile storage device 110, which per Han [0073] may be a plurality of devices, thus represents a plurality of dynamic capacity devices as the non-volatile storage may be dynamically allocated to the system as demand dictates.) and a processing device, (Han Fig. 8 and [0069] that discloses a central processing unit (CPU) 801 within electronic device 8000 that is one embodiment of the inventive concepts and is an example of a processing device.) operatively coupled with the memory device, to perform operations comprising: (Han Fig. 8 and [0069] discloses CPU 801 is coupled with Storing Unit 880.)
receiving a host command to combine first data associated with a first tag and second data associated with a second tag, (Han [0046] discloses at 502 a request to modify a part of the address mapping table included in a target profile is received, and [0052] discloses in one embodiment records of neighboring physical extents can be merged.) wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, wherein the second tag is associated with a second memory section of the plurality of dynamic capacity devices, (Consistent with para [0015] of the instant application a tag maps one or more contiguous address ranges. Han [0027] discloses that the system maintains a plurality of profiles including profile 302 that maps logical addresses to physical addresses, thus each profile is an example of a tag. Han [0027] discloses there may be a plurality of profiles, thus a first profile/tag associated with a first memory address and a second profile/tag associated with a second address.)
and wherein the first memory section is allocated to a first host system to store the first data and the second memory section is allocated to the first host system to store the second data; (Han Fig. 8 and [0069]-[0070] that discloses an embodiment that receives communication from external devices (where an external device may be a host). Han [0075] discloses that external device may be a single external computer. Thus the first memory section and the second memory section allocated to the first physical addresses and second physical addresses may be allocated to the first host (i.e. the single external host) served by the memory system of Fig. 1.)
and responsive to receiving the host command to combine: determining a third memory section of the plurality of dynamic capacity devices and associating a third tag with the third memory section; combining the first data and the second data into a combined data; and storing the combined data in the third memory section. (Examiner notes that no limitations are placed against the third memory section and the final location containing the combined data of a first tag and a second tag may be the third memory section. Han [0050] and [0052] discloses the system may determine that address mapping indicated by the profile in a request to modify an address mapping in a target profile containing first data may merge the requested updated information with the records of a neighboring physical extent containing a second profile, and create a third profile, thus creating a third memory section (i.e. a 3rd profile) which is stored in the address mapping table.)
Regarding claim 2, Han teaches all of the limitations of claim 1 above. Han further teaches wherein each of the plurality of memory sections is associated with a respective one of a plurality of tags, and wherein each of the plurality of tags is unique. (Han [0020] discloses that each logical block that is within a physical to logical mapping that is a tag contains a unique logical address (LBA), thus each plurality of tags that contains a LBA is unique.)
wherein each of the plurality of dynamic capacity devices comprises a plurality of memory sections, (Han [0020] discloses that each logical block is a logical storage space divided into continuous logical units where each logical block is an example of a memory section that makes up the non-volatile storage such as storage device 10 of Han Fig. 1.)
Regarding claim 9, Han teaches all of the limitations of claim 1 above. Han further teaches wherein the processing device is to perform operations further comprising: responsive to receiving a first allocation request from the first host system, determining the first memory section and associating the first tag with the first memory section; storing the first data in the first memory section; (Han Fig. 5 and para [0047]-[0049] discloses in response to a request to modify a part of the address mapping table the system first looks to identify an existing mapping entry (i.e. determining the first memory associated with the tag) and store the first data into the located mapping section.)
responsive to receiving a second allocation request from the first host system, determining the second memory section and associating the second tag with the second memory section; and storing the second data in the second memory section. (Han [0027] discloses there may be a plurality of mapping entries (mapping profiles). Thus there may be a second Han Fig. 5 cycle that requests to modify a second part of the address mapping table and updates a second mapping section.)
Regarding claim 13, Han teaches A method comprising: (Han [0003 ) receiving, by a processing device, (Han Fig. 8 and [0069] that discloses a central processing unit (CPU) 801 within electronic device 8000 that is one embodiment of the inventive concepts and is an example of a processing device.)
The remainder of claim 13 recites limitations described in claim 1 and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 14, Han teaches all of the limitations of claim 13 above.
The remainder of claim 14 recites limitations described in claim 2 and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 20, Han teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: (Han [0072]-[0073] teaches a computer program product that includes computer readable storage medium loaded with computer readable program instructions for executing various aspects of the disclosure.)
The remainder of claim 20 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Han (Han et al., US 2018/0300254 A1) as detailed in claim 1 above and further in view of Tardif (TARDIF US 2024/0394104 A1).
Regarding claim 8, Han teaches all of the limitations of claim 1 above. However, Han does not explicitly teach wherein the memory device comprises a compute express link (CXL) enabled memory device.
Tardif, of a similar field of endeavor, further teaches wherein the memory device comprises a compute express link (CXL) enabled memory device. (Tardif Fig. 1 and paras [0025]-[0026] discloses a that contains a bus system that connects client applications to memory systems using PCIE, CXL, Arm Microcontroller Bus Architecture (AMB), or other bus types in a system that provides address translation within a IOMMU, thus maintains an address translation table. Thus the solution of Han that includes an input/output bus 840 in a memory device would support a CXL bus as taught by Tardif given the CXL bus system is able to support a memory subsystem.
Han and Tardif are in a similar field of endeavor as both relate to supporting a memory device that provides address translations and include a bus to interface one or more processors with memory. Thus providing a simple substitution of one known element for another (i.e. substituting a specific bus implementation such as a CXL bus as detailed in Tardif for a generic bus interface as detailed in Han) to obtain predictable results (support a bus interface using an interface known to be supported by memory devices).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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