DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 August 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 7, 9, 11-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cong et al. (US 2019/0196977) in view of Gueron (“Memory Encryption for General-Purpose Processors”).
In regards to claims 1, 12, and 20, Cong teaches a system comprising:
a memory device comprising a plurality of dynamic capacity devices (“As illustrated in FIG. 1, in one embodiment, core 20A stores system MTM 80 in a portion of RAM 14 that has been reserved for error detection and/or correction purposes, such as one or more error-correcting code (ECC) memory chips or modules.”, paragraph 0033; “However, by using so-called ‘virtual memory’, an operating system (OS) in the data processing system may provide an apparent or virtual memory space that is larger than the actual physical memory. A conventional OS organizes virtual memory on the basis of fixed-size blocks known as ‘pages,’ and the OS uses page tables to map the virtual memory addresses to physical memory addresses. Accordingly, virtual memory allows different applications to use the same virtual address to access different physical addresses. The OS may also swap data from RAM out to a disk (or other mass storage device) when that data has not been accessed lately and the memory space is needed for other data.”, paragraphs 0002-0003); and
a processing device (processor 12, figure 1), operatively coupled with the memory device, to perform operations comprising:
receiving a host command to copy data (“However, when one of the processes (e.g., process 60A) does write to one of its pages, OS 70 may then create a new physical page, so that process 60A can access the modified version of the page, and process 60B can access the unmodified version of the page. Accordingly, OS 70 may determine that COW has been triggered in response to detecting that a process is writing to a shared page.”, paragraph 0056) associated with a first tag, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices (“As shown at block 412, OS 70 may then read the tags for the shared page from system MTM 80.”, paragraph 0079), and wherein the first memory section is allocated to a first host system to store the data (“Thus, memory protection module 34 uses system MTM 80 to store a tag for each line (in each physical page) that was allocated with memory tag protection. Thus, from the perspective of core 20A, memory controller 30 simply stores the tags inline with the data, in that memory controller 30 writes 64B of data to a physical address and also 1B of tag associated with that physical address in response to a single write request from core 20A.”, paragraph 0033);
responsive to receiving the host command to copy, determining a second memory section of the plurality of dynamic capacity devices (“As shown at block 408, OS 70 may then allocate a new physical page of memory.”, paragraph 0078) and associating a second tag with the second memory section (“For instance, if the tags are KeyIDs, memory protection module 34 may encrypt each line as it is written, using the key identified by the KeyID for that line.”, paragraph 0080); and
storing the copied data associated with the first tag in the second memory section associated with the second tag (Copy Content To New Page Using Tags 416, figure 3D).
Cong fails to teach that each of the first tag and the second tag is unique within an aggregate tag space of the memory device. Gueron teaches that each of the first tag and the second tag is unique within an aggregate tag space of the memory device (“Encrypting a data CL produces its ciphertext and uses or updates the metadata: a MAC tag and a ‘version’ counter. The version reflects the number of times the CL was written to the DRAM, information that’s critical for achieving ciphertexts’ semantic security over time.”, page 58, paragraph 6) in order to “protect data integrity and prevent replay” (page 56, paragraph 3, bullet 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cong with Gueron such that each of the first tag and the second tag is unique within an aggregate tag space of the memory device in order to “protect data integrity and prevent replay” (id.).
In regards to claims 2 and 13, Cong further teaches that each of the plurality of dynamic capacity devices comprises a plurality of memory sections (“A conventional OS organizes virtual memory on the basis of fixed-size blocks known as ‘pages,’”, paragraph 0003; “For purposes of this disclosure, when a page is subdivided into (or contains) two or more subdivisions, each subdivision may be referred to in general as a ‘subpage.’ And in particular, when a subpage is the same size as a cache line for cache memory in the data processing system, that subpage may be referred to as a ‘line.’”, paragraph 0017), wherein each of the plurality of memory sections is associated with a respective one of a plurality of tags (“In a data processing system that provides for memory protection with subpage granularity, different lines of a physical page may be protected with different memory tags.”, paragraph 0019), and wherein each of the plurality of tags is unique (“In particular, MTM 52A associates the tag value 0x0 with Line A, the tag value 0x1 with Lines B and C, the tag value 0xD with Line D, etc.”, paragraph 0041; “In one embodiment or scenario, each process maintains its own MTM, to keep track of which tags are assigned to which lines of virtual memory. In FIG. 1, the MTMs for processes 50A, 60A, and 60B are depicted as MTMs 52A, 62A and 62B, respectively. Thus, each process may use its MTM to associate different memory tag values with different lines of virtual memory for that process.”, paragraph 0031).
In regards to claims 3 and 14, Cong further teaches that the host command specifies the first tag (“As indicated above, when process 50A subsequently accesses any line, process 50A automatically supplies the proper tag value, since that tag value is embedded in the virtual address used by process 50A to access that line.”, paragraph 0054).
In regards to claims 6 and 17, Cong further teaches that a capacity of the first memory section allocated to the first host system and associated with the first tag is immutable (“And in particular, when a subpage is the same size as a cache line for cache memory in the data processing system, that subpage may be referred to as a ‘line.’”, paragraph 0017).
In regards to claims 7 and 18, Cong further teaches that the host command specifies at least one of: a region, of the plurality of dynamic capacity devices, for the second memory section (“In other words, when the OS kernel performs COW or SI/SO procedures for a page of physical memory, the OS may read or write each line individually, specifying the address for a line, along with a tag value for that line.”, paragraph 0020), or a selection policy for selecting the second memory section.
In regards to claim 9, Cong further teaches that the processing device is to perform operations further comprising:
responsive to receiving an allocation request from the first host system (“For instance, OS 70 may determine that a page needs to be swapped in, in response to process 50A attempting to read or write to a page that was swapped out.”, paragraph 0055), determining the first memory section (“As shown at block 316, OS 70 then populates a register or variable referred to herein as the ‘Destination_Page_Address’ with the physical address of the location in RAM 14 that is to receive the page of data that is being swapped back in (i.e., the physical address of the ‘returning page’).”, paragraph 0071) and associating the first tag with the first memory section (“As shown at block 318, OS 70 also stores the physical address of the pertinent portion of the MTM for the returning page in a register or variable referred to herein as ‘Tag_Map_Address.’”, paragraph 0071; “For example, the OS and/or the other software may need to maintain a memory tag map (MTM) for each process, to indicate which tag values are associated with different lines of memory for that process.”, paragraph 0019); and
storing the data in the first memory section (“As shown at block 320, OS 70 then invokes a special tag management instruction to copy a page of data from the temporary source page to the destination page.”, paragraph 0072).
In regards to claims 11 and 19, Cong further teaches that the processing device is to perform operations further comprising:
mapping the first tag, the first memory section, and an identifier of the first host system (“For example, the OS and/or the other software may need to maintain a memory tag map (MTM) for each process, to indicate which tag values are associated with different lines of memory for that process.”, paragraph 0019; “As indicated above, a conventional OS organizes virtual memory into pages, using page tables to map virtual memory to physical memory, and swapping data from RAM out to disk a page at a time.”, paragraph 0016).
Claims 4, 5, 8, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cong et al. (US 2019/0196977) in view of Gueron (“Memory Encryption for General-Purpose Processors”) and Choi et al. (US 2024/0231615).
In regards to claims 4 and 15, Cong in view of Gueron teaches claims 1 and 12. Cong in view of Gueron fails to teach that the host command is received from a second host system, wherein the host command specifies the second host system, and wherein the second memory section associated with the second tag is allocated to the second host system. Choi teaches that the host command is received from a second host system (“Using a logical address in the logical address range, the plurality of host processors 104A, 104B, 104C, 104D, . . . , 104# can access the memory areas allocated to the plurality of host processors 104A, 104B, 104C, 104D, . . . , 104#.”, paragraph 0053), wherein the host command specifies the second host system (“According to an embodiment, because the device allocation manager 330 can recognize which host uses or accesses the memory area or section, the device allocation manager 330 can transfer a message transmitted from the plurality of CXL endpoints 320A, 320B, 320C, . . . , 320N into the plurality of memory devices 310A, 310B, 310C, . . . , 310Z based on an identifier included in the message. … When the host transmits a command such as a read command, a write command, or an erase command to use or access the memory area, the host may transmit to the memory system 300 a message including the information regarding the allocated memory area or memory device along with the command. The memory system 300 may transfer the message to one among the plurality of memory devices 310A, 310B, 310C, . . . 310Z, based on the identifier included in the message.”, paragraph 0082), and wherein the second memory section associated with the second tag is allocated to the second host system (“When at least one from among the plurality of memory areas included in the plurality of memory devices 310A, 310B, 310C, . . . , 310Z is allocated to a specific host, the host may recognize information (e.g., physical address, identifier, or etc.) regarding the allocated memory area or memory device.”, paragraph 0082) in order “to overcome resource limitations in the computing system” (paragraph 0003). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cong with Gueron and Choi such that the host command is received from a second host system, wherein the host command specifies the second host system, and wherein the second memory section associated with the second tag is allocated to the second host system in order “to overcome resource limitations in the computing system” (id.).
In regards to claims 5 and 16, Choi further teaches that the first memory section is accessible by the first host system, and the second memory section is accessible by the second host system (“For example, a first memory device 310A may include a plurality of memory areas allocated to two or more hosts (e.g., 102A, 102B, 102C, etc.).”, paragraph 0080).
In regards to claim 8, Cong in view of Gueron teaches claim 1. Cong in view of Gueron fails to teach that the memory device comprises a compute express link (CXL) enabled memory device. Choi teaches that the memory device comprises a compute express link (CXL) enabled memory device (“The memory system can further include a plurality of Compute Express Link (CXL) endpoints, each endpoint selectively coupled to the at least one host.”, paragraph 0023) in order “to overcome resource limitations in the computing system” (paragraph 0003). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cong with Gueron and Choi such that the memory device comprises a compute express link (CXL) enabled memory device in order “to overcome resource limitations in the computing system” (id.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cong et al. (US 2019/0196977) in view of Gueron (“Memory Encryption for General-Purpose Processors”) and Han et al. (US 2024/0020174).
In regards to claim 10, Cong further teaches that the processing device is to perform operations further comprising:
creating the first tag responsive to receiving an allocation request by a node, wherein the node runs on the first host system (“In one embodiment or scenario, each process maintains its own MTM, to keep track of which tags are assigned to which lines of virtual memory. In FIG. 1, the MTMs for processes 50A, 60A, and 60B are depicted as MTMs 52A, 62A and 62B, respectively. Thus, each process may use its MTM to associate different memory tag values with different lines of virtual memory for that process.”, paragraph 0031).
Cong in view of Gueron fails to teach that the node is in an orchestrator cluster. Han teaches that the node is in an orchestrator cluster (“Workload orchestrator 250 is configured to monitor, manage, and maintain workloads instantiated on the processing nodes 210, 212, 214, and 216.”, paragraph 0020) in order “to reduce memory fragmentation, and to thereby improve performance” (paragraph 0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cong with Gueron and Han such that the node is in an orchestrator cluster in order “to reduce memory fragmentation, and to thereby improve performance” (id.).
Response to Arguments
Applicant’s arguments, see page 8, filed 10 August 2026, with respect to the drawing objections and 112(b) rejection have been fully considered and are persuasive. The drawing objections and 112(b) rejection have been withdrawn.
Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 28 September 2026
