Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 9-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cong et al (US20190196977, “Cong”).
As to claim 1, 12, 20:
Cong discloses a system (data processing system; 0002, 0018, 0023-0024; Fig .1), associated method of operation (instructions performing a method; 0021, 0063, claims 13-20), and associated computer readable medium including instructions for performing the method of the system; 0086) comprising:
a memory device comprising a plurality of dynamic capacity devices; (memory 14; Fig. 23; 0023; can be allocated/deallocated; 0037-0038; interpret dynamic capacity device as a memory device that can be allocated/deallocated, changing the capacity of usable storage); and a processing device (processor12; 0023-0024; Fig . 1), operatively coupled with the memory device, to perform operations comprising:
receiving a host command to freeze first data associated with a first tag, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data (data processing system performing allocation operations/commands and using tag to protect for a memory page; 0018, 0019, 0030; memory tag is assigned a specific tag value, the value is associated with a protection status; 0013, 0045);
responsive to receiving the host command to freeze, making the first data inaccessible to the first host system (in memory access operations, provide memory protection from access using with tag value; 0018, 0019, 0026, 0030); and
responsive to determining that the host command indicates to free the first memory section (for requests in copy on write operations, swap operations, memory deallocation/free operations; 0019), storing the first data in a second memory device, wherein the second memory device is not included in the plurality of dynamic capacity devices (in deallocation and free operation, copy data from one memory to another memory or to a disk, maintain memory tag map; 0065, 0019).
[Interpretation: based on claimed steps as a result of the “free” command, operation to store first data from one memory device to another memory device, “free” command is interpreted as an operation to copy first data from one location to another, such as copy on write/swap operation.]
As to claim 2, 13:
Cong teaches each of the plurality of dynamic capacity devices comprises a plurality of memory sections, wherein each of the plurality of memory sections is associated with a respective one of a plurality of tags, and wherein each of the plurality of tags is unique (each memory address page/block is associated with a unique tag value; 0014, 0016).
As to claim 3, 14:
Cong teaches the host command specifies the first tag (command with address includes tag value; 0015, 0020, 0021).
As to claim 4, 15:
Cong teaches the host command specifies whether to free the first memory section (operation to deallocate/free memory; 0019).
As to claim 5, 16:
Cong teaches the operations further comprise: responsive to determining that the host command indicates to free the first memory section, disassociating the first tag with the first memory section (free/deallocation function, tag value associated with memory is tracked and updated; 0019, 0052-0053).
As to claim 6, 17:
Cong teaches wherein a capacity of the first memory section allocated to the first host system and associated with the first flag is immutable (size of allocated page is fixed, such as 4K; 0030, 0034, 0051).
As to claim 7, 18:
Cong teaches making the first data inaccessible comprises setting an item of a tag mapping data structure to a predefined value (tag is set with has specific tag value to associate protection; 0014, 0045).
As to claim 9:
Cong teaches the operations further comprise: responsive to receiving a first allocation request from the first host system, determining the first memory section and associating the first tag with the first memory section; and storing the first data in the first memory section (allocating memory and associate tag with for protection; 0019, 0030, 0033; storing data; 0003, 0031.
As to claim 10:
Cong teaches the operations further comprise: creating the first tag responsive to receiving the first allocation request by a first node in an orchestrator cluster, wherein the first node runs on the first host system (allocate memory and create tag associating with memory; 0019, 0033, 0052; allocation request can be from different computing system in computing cluster; 0088).
As to claim 11, 19:Cong teaches the operations further comprise: responsive to determining that the host command indicates to free the first memory section, determining the second memory device (copy on write, swap operation; memory deallocation/free; 0019; copy data to another memory/disk).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cong et al (US20190196977, “Cong”), in view of Lee et al (US20230359379, “Lee”).
As to claim 8:
Cong teaches a memory device but does not specifically teach the memory device comprises a compute express link (CXL) enabled memory device. Cong does teach the memory is shared and protected using tag values; 0078, 0056, 0093). It is well-known in the art to use CXL memory and interconnect to communicate between shared memory to obtain data transfer with low latency. Lee teaches using a Compute Express Link storage and memory (0034) wherein the shared memory communicate with low latency and high bandwidth that support coherency (0040). It would have been obvious to one of ordinary skills in the art, at the time of the invention, to use Lee’s teaching of using CXL memory, for the shared memory of Cong, so that the shared memory access can have low latency and high bandwidth.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20160378668 discloses techniques for embedding information about memory accesses to a memory module at the memory module itself. The information, referred to herein as “access metadata,” can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like.
US20230350832 discloses a storage device includes a nonvolatile memory device that stores user data, and a storage controller that controls the nonvolatile memory device based on control of a host device. The storage controller includes a storage interface circuit that communicates with the host device through a compute express link (CXL) interface, a NAND interface circuit that communicates with the nonvolatile memory device, and a processor that loads map data from an external memory device placed outside the storage device through the storage interface circuit and controls the nonvolatile memory device through the NAND interface circuit based on the map data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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