CTNF 19/211,835 CTNF 88147 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (lDS) submitted are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over EGAWA; Yoshitaka (US 20120199723 A1, hereinafter “ EGAWA ”), in view of Kobayashi; Hideo (US 20220303484 A1, hereinafter “ Kobayashi ”) . Regarding claim 1 , EGAWA teaches a photoelectric conversion device ( Figs. 1-2: a pixel array unit 1-1 ) comprising: a pixel including a photoelectric conversion unit ( Figs. 1-2: a photoelectrically-converted charge being accumulated in a pixel PC ) and an output unit ( Figs. 1-2: a row selecting transistor Ta, an amplification transistor Tb ) configured to output a signal based on charge generated in the photoelectric conversion unit ( Figs. 1-2: Because the source follower is constructed by the amplification transistor Tb and the load transistor TL, the voltage at the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb to be output to the vertical signal line Vlin as the output voltage Vsig of the read level. ); a signal output line connected to the pixel ( Figs. 1-2: vertical signal line Vlin ); a level shift circuit connected to the signal output line ( Figs. 1-2: level-shift circuit 10-2 ) and configured to perform a level-shift on an output signal of the pixel ( Figs. 1-2: the level-shift circuits 10-1 shifts a potential at the vertical signal line Vlin ) in a direction in which a voltage decreases ( Figs. 2-3, [0048]: switching signal PBL is applied to turn on the level-shift circuit, and the output voltage Vsig of the vertical signal line Vlin is shifted from a steady voltage Vr by a shift voltage Vb. ); and a signal processing circuit connected to the level shift circuit ( Figs. 1-2: column ADC circuit 4 ) and oversampling-type analog- to-digital conversion including a capacitor ( Figs. 1-2: the column ADC circuit 4 and capacitor C1 ) to which an output signal of the level shift circuit is input (Figs. 1-2: Vsig), wherein the signal processing circuit includes an oversampling-type analog- to-digital conversion circuit ( Figs. 1-2: the column ADC circuit 4 ). EGAWA does not teach the analog- to-digital conversion is an oversampling-type . However, Kobayashi discloses the analog- to-digital conversion is an oversampling-type ([ 0035]: One conversion unit 60 is provided for each sample and hold unit 50. The conversion unit 60 is an A/D converter circuit that analog-to-digital converts a signal output from the corresponding sample and hold unit 50 and outputs a digital signal. Specific examples of an A/D converter circuit include a slope analog-to-digital conversion circuit, a successive-approximation analog-to-digital conversion circuit, a delta-sigma (ΔΣ) analog-to-digital conversion circuit, and the like. However, the A/D converter circuit is not limited thereto. ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the analog- to-digital conversion is an oversampling-type as taught by Kobayashi into EGAWA photoelectric conversion device. The suggestion/ motivation for doing so would be to output an analog-to-digital conversion output with high accuracy ( Kobayashi : [0058]). Regarding claim 2 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, in addition EGAWA discloses wherein a second power supply voltage supplied to the signal processing circuit is lower than a first power supply voltage supplied to the output unit ( as illustrated by Fig. 3: Vsig and a power supply potential VDD ). Regarding claim 3 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, in addition EGAWA discloses wherein the signal processing circuit further includes a comparison circuit to which the output signal of the level shift circuit is input via the capacitor ( as illustrated by Fig. 2, [0037]: capacitors C1 and a comparator PA, ). Regarding claim 4 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, in addition Kobayashi discloses wherein the signal processing circuit includes a sample-and-hold circuit including the capacitor ( as illustrated by Figs. 1&3, [0029]&[0034]: a photoelectric conversion device 1000 including a sample and hold unit (SH) 50, a conversion unit (AD) 60, a data processing circuit 90, and an output circuit 100 ) . The suggestion/ motivation for doing so would be to improve signal-to-noise ratio (SNR) across the image sensor. Regarding claim 19 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, in addition EGAWA discloses wherein the pixel comprises a plurality of pixels arranged to form a plurality of columns, wherein the signal output line comprises a plurality of signal output lines, at least one of the plurality of output lines is provided for each of the plurality of columns, and each of the plurality signal output lines is connected to the pixels on the corresponding column ( as illustrated by Figs. 1-2: a pixel array unit 1-1 in which pixels PC are two-dimensionally arrayed in a row direction and a column direction. Vertical lines Vin ), and wherein the level shift circuit and the signal processing circuit are provided corresponding to each of the plurality of signal output lines ( as illustrated by Figs. 1-2: Lines Vin, Level-shift circuit and column ADC ) . 07-21-aia AIA Claim s 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over EGAWA and Kobayashi combination as applied above, in view of Yamashita et al. (US 20130248688 A1, hereinafter “ Yamashita ”) . Regarding claim 5 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, except wherein the signal processing circuit includes a gain amplifier including the capacitor. Yamashita discloses wherein the signal processing circuit includes a gain amplifier including the capacitor ( as illustrated by Figs. 1-2, [0033]-[0036]: The column circuit 107 may include an amplifier circuit 200a in a previous stage and an amplifier circuit 200b in a subsequent stage. Each of the amplifier circuits 200a and 200b may include an operational amplifier circuit. ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the signal processing circuit includes a gain amplifier including the capacitor as taught by Yamashita with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to reduce noise which yield highly accurate, clear image readouts. Regarding claim 6 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, except wherein the signal processing circuit includes a switched capacitor circuit including the capacitor. Yamashita discloses wherein the signal processing circuit includes a switched capacitor circuit including the capacitor ( as illustrated by Figs. 1-2, [0033]-[0036]: A switch P11 and a first feedback capacitor C11 are provided on a second feedback path. A switch P12 and a second feedback capacitor C12 are provided on a third feedback path. ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the signal processing circuit includes a switched capacitor circuit including the capacitor as taught by Yamashita with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to reduce noise which yield highly accurate, clear image readouts . 07-21-aia AIA Claim s 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over EGAWA and Kobayashi combination as applied above, in view of Ebihara et al. (US 20210021774 A1, hereinafter “ Ebihara ”) . Regarding claim 7 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, except wherein the level shift circuit is configured to supply a current to the signal processing circuit. However, Ebihara discloses wherein the level shift circuit is configured to supply a current to the signal processing circuit ( as illustrated by Figs. 1&6, [0036]-[0038]: level shifter 660A includes a source follower 662 that works as a level shifter ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the level shift circuit is configured to supply a current to the signal processing circuit as taught by Ebihara with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to reduce noise which yield highly accurate, clear image readouts. Regarding claim 8 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1, except wherein the level shift circuit includes a source follower circuit having an input node to which the output signal of the pixel is input and an output node connected to the signal processing circuit. However, Ebihara discloses wherein the level shift circuit includes a source follower circuit having an input node to which the output signal of the pixel is input and an output node connected to the signal processing circuit ( as illustrated by Figs. 1&6, [0036]-[0038]: the gate input of the source follower 662 is coupled to the Vamp 628 voltage node of column amplifier 604A, and output of the source follower 662 of level shifter 660 is coupled to the amplifier auto-zero switch 626 connected to the Vin. ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the level shift circuit includes a source follower circuit having an input node to which the output signal of the pixel is input and an output node connected to the signal processing circuit as taught by Ebihara with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to reduce noise which yield highly accurate, clear image readouts. Regarding claim 9 , EGAWA, Kobayashi and Ebihara combination teaches the photoelectric conversion device according to claim 8, except wherein a back gate of a transistor constituting the source follower circuit is connected to a source of the transistor. However, Ebihara discloses wherein a back gate of a transistor constituting the source follower circuit is connected to a source of the transistor ( as illustrated by Figs. 1&6, [0036]-[0038]: the level shifter current source 664B in the level shifter 660B is shown being implemented as an NMOS current source coupled to source follower input device 662. In other words, the level shifter current source 664A shown in FIG. 6A is replaced by a NMOS device 664B in FIG. 6B. The gate and drain of the NMOS device 664B are coupled to the output of the source follower 662. ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide wherein a back gate of a transistor constituting the source follower circuit is connected to a source of the transistor as taught by Ebihara with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to reduce noise which yield highly accurate, clear image readouts . 07-21-aia AIA Claim s 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over EGAWA and Kobayashi combination as applied above, in view of Yamazaki; Kazuo (US 20220303491 A1, hereinafter “ Yamazaki ”) . Regarding claim 20 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1; except a movable object comprising: a distance information acquisition unit configured to acquire distance information to an object from a parallax image based on a signal from the photoelectric conversion device; and a control unit configured to control the movable object based on the distance information. However, Yamazaki a movable object ( as illustrated by Figs. 9-11, [0162]: a movable object ) comprising: discloses a distance information acquisition unit configured to acquire distance information to an object from a parallax image based on a signal from the photoelectric conversion device; and a control unit configured to control the movable object based on the distance information ( as illustrated by Fig. 10, [0163]: parallax acquisition unit 314 and the distance acquisition unit 316 are an example of a distance information acquisition unit that acquires distance information to the object. That is, the distance information is information related to parallax, defocus amount, distance to the object, and the like. The collision determination unit 318 may determine the possibility of collision using any of the distance information. ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a movable object comprising: a distance information acquisition unit configured to acquire distance information to an object from a parallax image based on a signal from the photoelectric conversion device; and a control unit configured to control the movable object based on the distance information as taught by Yamazaki with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to increase the value of the equipment EQP ( Yamazaki : [0174]). Regarding claim 21 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1; except a photoelectric conversion system comprising: a signal processing device configured to process a signal output from the photoelectric conversion device However, Yamazaki discloses a photoelectric conversion system ( as illustrated by Figs. 9-11, [0163]: imaging system) comprising: a signal processing device configured to process a signal output from the photoelectric conversion device ( as illustrated by Figs. 9-11, [0163]: image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310 ) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a photoelectric conversion system comprising: a signal processing device configured to process a signal output from the photoelectric conversion device as taught by Yamazaki with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to produce a digital image. Regarding claim 22 , EGAWA and Kobayashi combination teaches the photoelectric conversion device according to claim 1; except an equipment comprising: at least one of an optical device corresponding to the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process a signal output from the photoelectric conversion device, a mechanical device that is controlled based on information obtained by the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, and a storage device configured to store information obtained by the photoelectric conversion device. Yamazaki discloses an equipment ( as illustrated by Figs. 9-11: an equipment ) comprising: at least one of an optical device corresponding to the photoelectric conversion device ( as illustrated by Figs. 9-11, [0171]: optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror ), a control device configured to control the photoelectric conversion device ( as illustrated by Figs. 9-11, [0171]: control device CTRL controls the photoelectric conversion device APR ), a processing device configured to process a signal output from the photoelectric conversion device ( as illustrated by Figs. 9-11, [0171]: processing device PRCS processes a signal output from the photoelectric conversion device APR ), a mechanical device that is controlled based on information obtained by the photoelectric conversion device ( as illustrated by Figs. 9-11, [0156]: mechanical device MCHN in the camera may drive components of the optical device OPT for zooming, focusing, and shutter operation ), a display device configured to display information obtained by the photoelectric conversion device ( as illustrated by Figs. 9-11, [0171]: a signal output from the photoelectric conversion device APR is displayed on the display device DSPL ), and a storage device configured to store information obtained by the photoelectric conversion device ( as illustrated by Figs. 9-11, [0171]: a storage device MMRY is a magnetic device or a semiconductor device that stores information (image) obtained by the photoelectric conversion device APR ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an equipment comprising: at least one of an optical device corresponding to the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process a signal output from the photoelectric conversion device, a mechanical device that is controlled based on information obtained by the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, and a storage device configured to store information obtained by the photoelectric conversion device as taught by Yamazaki with EGAWA and Kobayashi combination. The suggestion/ motivation for doing so would be to increase the value of the equipment EQP ( Yamazaki : [0174]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 10-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Contact 07-101 Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204 . The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.usp to. gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000 . /ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638 Application/Control Number: 19/211,835 Page 2 Art Unit: 2638 Application/Control Number: 19/211,835 Page 3 Art Unit: 2638 Application/Control Number: 19/211,835 Page 4 Art Unit: 2638 Application/Control Number: 19/211,835 Page 5 Art Unit: 2638 Application/Control Number: 19/211,835 Page 6 Art Unit: 2638 Application/Control Number: 19/211,835 Page 7 Art Unit: 2638 Application/Control Number: 19/211,835 Page 8 Art Unit: 2638 Application/Control Number: 19/211,835 Page 9 Art Unit: 2638 Application/Control Number: 19/211,835 Page 10 Art Unit: 2638 Application/Control Number: 19/211,835 Page 11 Art Unit: 2638 Application/Control Number: 19/211,835 Page 12 Art Unit: 2638 Application/Control Number: 19/211,835 Page 13 Art Unit: 2638 Application/Control Number: 19/211,835 Page 14 Art Unit: 2638
Prosecution Insights