DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new grounds of rejection. See Office Action below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 9-10, 15, & 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI et al. (US Pub. No. 2023/0289074 A1) in view of Dubeyko et al. (US Pub. No. 2023/0359591 A1).
In respect to Claim 1, CHOI teaches:
a system comprising: a memory device comprising a plurality of dynamic capacity devices; (CHOI teaches [0018, 0044] a CXL dynamic memory capacity expansion device whose capacity is increased/decreased dynamically.)
wherein the first file system data is stored in a first memory section of a plurality of memory sections of the plurality of dynamic capacity devices, wherein the first memory section is associated with a first tag; (CHOI teaches [0053] a dynamic capacity expansion list includes a HDM TAG with block information related to the memory block in regions N and N + 1.)
Dubeyko teaches:
and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving, from a host system, a request to perform a computational operation on first file system data, wherein the request comprises an identifier of the first file system data and specifies the computational operation, (Dubeyko teaches [0029] a host side file system driver may prepare one or several journal transactions. Every transaction may contain a set or range of LBAs and a function to execute this computation and [0019, 0033] the responsibility of file system is only to identify data or metadata that needs to be processed, the type of data in these LBAs, and a function or algorithm that needs to be applied.)
performing the computational operation on the first file system data to obtain second data; (Dubeyko teaches [0030] the FPGA cores may extract LBA numbers from a metadata area of the transaction and execute the function for every LBA number in the request.)
determining a second memory section of the plurality of dynamic capacity devices and associating the second memory section with a second tag; (Dubeyko teaches [0030-0031, 0040, 0045] the result of execution can be delivered on the host side as a result of read operation, can be stored into another set of LBA numbers, or can be stored as update of the requested set of LBA numbers, wherein determining a second location is analogous to the above teaching.)
and storing the second data in the second memory section associated with the second tag (Dubeyko teaches [0030, 0045] storing the computations result into another set of LBA numbers, wherein this is storing a computed result in a distinct and designated location.)
It would have been obvious to one of ordinary skill in the art at the time of the filing date of the invention to incorporate the teachings of Dubeyko into the system of CHOI. One of ordinary skill in the art would be motivated to provide improved techniques for data processing a large quantity of data processing tasks. (Dubeyko [0001]).
As per Claim 6, CHOI teaches:
wherein each of the plurality of memory sections is associated with a respective one of a plurality of tags (CHOI [0053])
As per Claim 9, CHOI teaches:
wherein the memory device is a compute express link (CXL) enabled memory device (CHOI [Abstract])
Claims 10 & 15 are the method claims corresponding to system claims 1 & 6 respectively, therefore are rejected for the same reasons noted previously.
Claim 17 is the media claim corresponding to system claim 1 above, therefore is rejected for the same reasons noted previously.
Claim(s) 2-3, 11-12, & 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI & Dubeyko, and further in view of Kesavan et al. (US Pub. No. 2021/0328593 A1).
CHOI teaches:
determining, based on the identifier of the first file system data, that the first file system data is stored in a first memory section of the plurality of dynamic capacity devices, wherein the first memory section is associated with a first tag; (CHOI teaches [0053] a dynamic capacity expansion list includes a HDM TAG with block information related to the memory block in regions N and N + 1.)
Kesavan teaches:
determining that the first memory section stores a value indicating the first memory section implements a file system; (Kesavan teaches [0016] the page comprises a file system superblock; the file system superblock is a root of a file system tree of the file system for the persistent memory, with a duplicate copy of the file system superblock maintained withing another page of the persistent memory for redundancy.)
and determining that the first file system data is file data of file system data for the file system, wherein the file system data comprises the file data and file metadata (Kesavan teaches [0018, 0095] organizing file content via an inode/page tree structure, wherein each inode stores a location of a root of a file tree for a given file; direct block of the file tree of the file comprise the actual user date.)
It would have been obvious to one of ordinary skill in the art at the time of the filing date of the invention to incorporate the teachings of Kesavan into the systems of CHOI and Dubeyko. One of ordinary skill in the art would be motivated to provide a system with the ability to store data within byte addressable storage types despite different access characteristics of these types of byte addressable storage in terms of performance and persistence semantics. (Kesavan [0002])
As per Claim 3, Kesavan teaches:
wherein the value is stored in a first portion of the first memory section, and wherein the value comprises a flag indicating whether the first memory section contains different portions designated for different data types in the file system (Kesavan teaches [0016, 0093] a superblock which occupies a specific, define page; wherein this is a fixed, known first portion of the memory region which necessitates the region is organized into designated portions such as superblock pages, inode/inofile pages, and data pages.)
It would have been obvious to one of ordinary skill in the art at the time of the filing date of the invention to incorporate the teachings of Kesavan into the systems of CHOI and Dubeyko. One of ordinary skill in the art would be motivated to provide a system with the ability to store data within byte addressable storage types despite different access characteristics of these types of byte addressable storage in terms of performance and persistence semantics. (Kesavan [0002])
Claims 11-12 are the method claims corresponding to system claims 2-3 respectively, therefore are rejected for the same reasons noted previously.
Claims 18-19 are the media claims corresponding to system claims 2-3 respectively, therefore are rejected for the same reasons noted previously.
Claim(s) 4, 13, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI & Dubeyko, and further in view of Kimmel et al. (US Pub. No. 2015/0205680 A1).
As per Claim 4, Kimmel teaches:
wherein the file metadata is stored in one or more entries of a log in a second portion of the first memory section, wherein the log comprises a plurality of entries, (Kimmel teaches [0037] that the extent store layer may also maintain a dedicated log of entries that accumulate requested put and delete operation (i.e., write request and delete requests for extents issued from other layers to the extent store layer), where these operations change the in-core mappings (i.e., hash table entries))
wherein the file data is stored in one or more extents in a third portion of the first memory section, and wherein the third portion comprises a plurality of extents (Kimmel teaches [0036] that an extent is a variable length block of data that provides a unit of storage on the SSDs, it may be byte aligned, and the persistence layer may aggregate the organize write data from one or more write requests into a new extent.)
It would have been obvious to one of ordinary skill in the art at the time of the filing date of the invention to incorporate the teachings of Kimmel into the systems of CHOI & Dubeyko. One of ordinary skill in the art would be motivated to provide storage systems for efficient logging and checkpointing of metadata in a storage system. (Kimmel [0002])
Claim 13 is the method claim corresponding to system claim 4 above, therefore is rejected for the same reasons noted previously.
Claim 20 is the media claim corresponding to system claim 4 above, therefore is rejected for the same reasons noted previously.
Claim(s) 7-8 & 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI & Dubeyko, and further in view of Price et al. (US Pub. No. 2024/0037026 A1).
As per Claim 7, CHOI teaches:
wherein a capacity of the first memory section is immutable, (CHOI teaches [0052] fixed sized block units.)
Price teaches:
and wherein the first tag is mapped to the first memory section and an identifier of the host system (Price teaches [0037] the pool manager may maintain an allocation table that indicates which memory resources in the memory pool have been allocated to which processing resources, and separately, [0049] the global shared state may include memory provisioning information indicating portions of the external memory resources that are owned by individual host computing devices.)
It would have been obvious to one of ordinary skill in the art at the time of the filing date of the invention to incorporate the teachings of CHOI & Dubeyko into the system of Price. One of ordinary skill in the art would be motivated to provide techniques for memory pooling, provisioning, and sharing.
As per Claim 8, Price teaches:
mapping, to the second tag, the second memory section, and an identifier of the host system (Price teaches [0037] the pool manager may maintain an allocation table that indicates which memory resources in the memory pool have been allocated to which processing resources, and separately, [0049] the global shared state may include memory provisioning information indicating portions of the external memory resources that are owned by individual host computing devices, wherein the host to memory resource mapping mechanism applies to whichever tag or section is at issue, including the second (output) tag or section this element recites.)
It would have been obvious to one of ordinary skill in the art at the time of the filing date of the invention to incorporate the teachings of CHOI & Dubeyko into the system of Price. One of ordinary skill in the art would be motivated to provide techniques for memory pooling, provisioning, and sharing.
Claim 16 is the method claim corresponding to system claim 7 above, therefore is rejected for the same reasons noted previously.
Allowable Subject Matter
Claims 5 & 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA BULLOCK whose telephone number is (571)270-1395. The examiner can normally be reached 8:00 am - 4:00 pm.
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/JOSHUA BULLOCK/Primary Examiner, Art Unit 2153 September 19, 2026
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