DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to amendment of application on 8-SEPT-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8-SEPT-2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 7-8, filed 8-SEPT-2026, with respect to objections to claims have been fully considered and are persuasive due to amendments. The objections to claims 2, 11, and 17 have been withdrawn.
Applicant’s arguments, see pages 8-9, filed 8-SEPT-2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C 102 and 35 U.S.C. 103 have been fully considered and are persuasive due to amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art references.
1. Regarding Applicant’s arguments that Examiner allegedly agreed that the cited art failed to disclose certain features in the September 4th interview, Examiner notes that no such agreement from the Examiner ever occurred. According to Applicant’s own summary of the interview, “no specific agreement was reached”, which is consistent with Examiner’s Interview Summary filed 9-SEPT-2026, which records that, at most, “Examiner suggested several avenues to amend the claims to better include the elements which Applicant’s Representative argued distinguishes from the prior art, but noted that overcoming the prior art would depend on how such amendments were drafted.” Examiner further notes that the interview agenda for the September 4th interview did not even include any proposed amendments, and accordingly, there would not have even been a particular drafting for Examiner to agree upon within the time allotted for the interview. As this is the only argument Applicant makes to address the rejections under the prior art, the arguments themselves are not persuasive.
2. Regardless of Applicant’s arguments alleging an agreement, the independent claims have been amended in a manner which does overcome the previously cited prior art reference, by clarifying a particular physical arrangement of elements which perform the described functions, and the rejections are therefore updated to address the newly amended claims below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7-10, 13-14, 16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Golov, U.S. Pub. No. 20220129394 (hereinafter “Golov”) in view of
KANNO, U.S. Pub. No. 20170262228 (hereinafter “Kanno”).
Regarding claim 1: Golov teaches A host system comprising:
A memory; and a processing device, operatively coupled with the memory, to perform operations comprising: ([0015-0016], Golov teaches a system with a memory and host processor as an example physical embodiment.).
Sending, to a controller of a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections ([0019-0022], Golov teaches that a memory controller may receive a request to write data to the memory array from a host processor, and that the memory may include a plurality of regions (memory sections) defined as ranges of addresses in the memory array. Further, in [0068], Golov teaches that a memory array may be composed of a number of banks.)
Accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of tags ([0023-0025] and [0043], Golov teaches that memory accesses reference a configuration table that stores a mapping of region identifiers to specific addressed regions of memory (aggregated DPA ranges, each associated with a tag, used to access data), which is queried by a host processor’s hypervisor in order to initialize a mapping within the hypervisor, and therefore is an aggregation by the host system.)
While Golov teaches the usage of various mappings on configuration tables that can be found on the host side, and generally teaches some level of updating the mappings when performing operations, Golov does not appear to explicitly disclose receiving, from the controller of the memory device, a response to the request, wherein the response comprises a set of tags in an order associated with the data, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of data; or the mapping the tags to logical addresses of the data being done by the host processor; and.
However, Kanno teaches receiving, from the controller of the memory device, a response to the request, wherein the response comprises a set of tags in an order associated with the data, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of data; mapping the tags to logical addresses of the data ([0410-0413], [0090-0092], and [0183], Kanno teaches a procedure for processing a host write command for a namespace ID (NSID, interpreted as a tag and corresponding to the Region IDs of Golov) for a namespace (a respective memory section associated with the NSID/tag), wherein the SSD which has a controller that accesses the storage of the SSD (controller of the memory device) sends a command completion response to the write command to the host (host system receiving) which includes the NSID, which the host will then use to update an address translation table corresponding to the NSID (mapping to a tag) to correctly map corresponding LBAs (logical addresses) which contains the data written during the write command processing. The broadest reasonable interpretation of ”a set of tags in an order associated with the data” is interpreted to comprise any amount of any tags in any non-specific order or arrangement.)
Golov and Kanno are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Kanno to achieve the result of a host system which sends requests to store data to a memory device and receives a response with a tag, wherein each tag is associated with a respective memory section of the plurality of memory sections and is mapped by the host to logical addresses, wherein the respective memory section stores a respective portion of data, and which access the data by aggregating some association of device physical address ranges associated with a respective tag.
One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the updating of mappings stored on the host side to correctly represent new data being written as discussed in Kanno [0413].
Regarding claim 4: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 4 depends.
Golov/Kanno further teaches each tag of the tags is unique (Golov Claim 6, Golov explicitly describes mappings being done to a plurality of unique corresponding region identifiers. Further, in Fig. 1 and [0022-0024], the listed regions are described following an ascending pattern, with each entry having its own ID).
Regarding claim 5: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 5 depends.
Golov/Kanno further teaches a size of each memory section allocated to the host system and associated with a respective tag is immutable (As described with respect to claim 1 and in [0038], Golov teaches memory regions (memory section) with region IDs (tags) mapped to VMs (host). Further, in [0022], Golov teaches that the size of the regions may be a constant size.)
Regarding claim 7: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 7 depends.
Golov/Kanno further teaches storing, in a host mapping data structure, the tags and the logical addresses ([0023-0028], Golov teaches that there may be mapping logic for the controllers which describe logical addresses to physical address mappings and region IDs.)
Regarding claim 8: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 8 depends.
Golov/Kanno further teaches generating an aggregation identifier that collectively identifies the tags associated with the data ([0037], Golov teaches maintaining a VM configuration table which maps VM identifiers (aggregation identifiers) to region IDs (tags associated with the data) that the VMs are mapped to.)
Regarding claim 9: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 9 depends.
Golov/Kanno further teaches storing, in a host mapping data structure, the tags, the logical addresses, and the aggregation identifier (Figs. 1 and 2, [0023-0028], and [0037], Golov teaches various information that the host processor maintains for mappings, which describes logical address to physical address mappings, region ID mappings, and VM identifier mappings.)
Regarding claim 10: Golov teaches A method comprising:
Sending, to a controller of a memory device, a request to store data in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections ([0019-0022], Golov teaches that a memory controller may receive a request to write data to the memory array from a host processor, and that the memory may include a plurality of regions (memory sections) defined as ranges of addresses in the memory array. Further, in [0068], Golov teaches that a memory array may be composed of a number of banks.)
Accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of tags ([0023-0025], Golov teaches that memory accesses reference a configuration table that stores a mapping of region identifiers to physical address ranges (aggregated DPA ranges, each associated with a tag, used to access data).)
While Golov teaches the usage of various mappings on configuration tables that can be found on the host side, and generally teaches some level of updating the mappings when performing operations, Golov does not appear to explicitly disclose receiving, from the controller of the memory device, a response to the request, wherein the response comprises a set of tags in an order associated with the data, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of data; or the mapping the tags to logical addresses of the data being done by the host processor; and.
However, Kanno teaches receiving, from the controller of the memory device, a response to the request, wherein the response comprises a set of tags in an order associated with the data, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of data; mapping the tags to logical addresses of the data ([0410-0413], [0090-0092], and [0183], Kanno teaches a procedure for processing a host write command for a namespace ID (NSID, interpreted as a tag and corresponding to the Region IDs of Golov) for a namespace (a respective memory section associated with the NSID/tag), wherein the SSD which has a controller that accesses the storage of the SSD (controller of the memory device) sends a command completion response to the write command to the host (host system receiving) which includes the NSID, which the host will then use to update an address translation table corresponding to the NSID (mapping to a tag) to correctly map corresponding LBAs (logical addresses) which contains the data written during the write command processing. The broadest reasonable interpretation of ”a set of tags in an order associated with the data” is interpreted to comprise any amount of any tags in any non-specific order or arrangement.)
Golov and Kanno are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Kanno to achieve the result of a host system which sends requests to store data to a memory device and receives a response with a tag, wherein each tag is associated with a respective memory section of the plurality of memory sections and is mapped by the host to logical addresses, wherein the respective memory section stores a respective portion of data, and which access the data by aggregating some association of device physical address ranges associated with a respective tag.
One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the updating of mappings stored on the host side to correctly represent new data being written as discussed in Kanno [0413].
Regarding claim 13: The combination of Golov and Kanno teaches all limitations of claim 10, from which claim 13 depends.
Golov/Kanno further teaches each tag of the tags is unique (Golov Claim 6, Golov explicitly describes mappings being done to a plurality of unique corresponding region identifiers. Further, in Fig. 1 and [0022-0024], the listed regions are described following an ascending pattern, with each entry having its own ID).
Regarding claim 14: The combination of Golov and Kanno teaches all limitations of claim 10, from which claim 14 depends.
Golov/Kanno further teaches a size of each memory section allocated to the host system and associated with a respective tag is immutable (As described with respect to claim 10 and in [0038], Golov teaches memory regions (memory section) with region IDs (tags) mapped to VMs (host). Further, in [0022], Golov teaches that the size of the regions may be a constant size.)
Regarding claim 16: Golov teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: ([0091-0094], Golov teaches an example embodiment of the invention of Golov which is a non-transitory machine readable medium with information to be executed by a computing device to perform the various methods.).
Sending, to a controller of a memory device, a request to store data in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections ([0019-0022], Golov teaches that a memory controller may receive a request to write data to the memory array from a host processor, and that the memory may include a plurality of regions (memory sections) defined as ranges of addresses in the memory array. Further, in [0068], Golov teaches that a memory array may be composed of a number of banks.)
Accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of tags ([0023-0025], Golov teaches that memory accesses reference a configuration table that stores a mapping of region identifiers to physical address ranges (aggregated DPA ranges, each associated with a tag, used to access data).)
While Golov teaches the usage of various mappings on configuration tables that can be found on the host side, and generally teaches some level of updating the mappings when performing operations, Golov does not appear to explicitly disclose receiving, from the controller of the memory device, a response to the request, wherein the response comprises a set of tags in an order associated with the data, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of data; or the mapping the tags to logical addresses of the data being done by the host processor; and.
However, Kanno teaches receiving, from the controller of the memory device, a response to the request, wherein the response comprises a set of tags in an order associated with the data, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of data; mapping the tags to logical addresses of the data ([0410-0413], [0090-0092], and [0183], Kanno teaches a procedure for processing a host write command for a namespace ID (NSID, interpreted as a tag and corresponding to the Region IDs of Golov) for a namespace (a respective memory section associated with the NSID/tag), wherein the SSD which has a controller that accesses the storage of the SSD (controller of the memory device) sends a command completion response to the write command to the host (host system receiving) which includes the NSID, which the host will then use to update an address translation table corresponding to the NSID (mapping to a tag) to correctly map corresponding LBAs (logical addresses) which contains the data written during the write command processing. The broadest reasonable interpretation of ”a set of tags in an order associated with the data” is interpreted to comprise any amount of any tags in any non-specific order or arrangement.)
Golov and Kanno are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Kanno to achieve the result of a host system which sends requests to store data to a memory device and receives a response with a tag, wherein each tag is associated with a respective memory section of the plurality of memory sections and is mapped by the host to logical addresses, wherein the respective memory section stores a respective portion of data, and which access the data by aggregating some association of device physical address ranges associated with a respective tag.
One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the updating of mappings stored on the host side to correctly represent new data being written as discussed in Kanno [0413].
Regarding claim 19: The combination of Golov and Kanno teaches all limitations of claim 16, from which claim 19 depends.
Golov/Kanno further teaches each tag of the tags is unique (Golov Claim 6, Golov explicitly describes mappings being done to a plurality of unique corresponding region identifiers. Further, in Fig. 1 and [0022-0024], the listed regions are described following an ascending pattern, with each entry having its own ID).
Regarding claim 20: The combination of Golov and Kanno teaches all limitations of claim 16, from which claim 20 depends.
Golov/Kanno further teaches a size of each memory section allocated to the host system and associated with a respective tag is immutable (As described with respect to claim 16 and in [0038], Golov teaches memory regions (memory section) with region IDs (tags) mapped to VMs (host). Further, in [0022], Golov teaches that the size of the regions may be a constant size.)
Claims 2-3, 11-12, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over
Golov, U.S. Pub. No. 20220129394 (hereinafter “Golov”) in view of
KANNO, U.S. Pub. No. 20170262228 (hereinafter “Kanno”) further in view of
Jiang et al., U.S. Pub. No. 20230152994 (hereinafter “Jiang”).
Regarding claim 2: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 2 depends.
Golov/Kanno further teaches sending, to the controller of the memory device, a first portion of the data, wherein a first memory section of the plurality of memory sections stores the first portion of the data ([0024-0027], Golov teaches the processing of write commands to store data into allocated memory regions)
Golov/Kanno further teaches wherein the first portion of the data is in a first predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov/Kanno further teaches wherein the second memory section is associated with a second tag ([0023] and [0038], Golov teaches the mapping of memory regions to region IDs, and specifically that there are assigned region IDs for regions that are not even allocated yet, thereby rendering obvious a second memory section with a second tag.)
Golov/Kanno further teaches wherein the second portion of the data is in a second predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov/Kanno further teaches wherein mapping the tags to the logical addresses of the data is performed responsive to determining that the sum of the first predefined size and the second predefined size is not less than the size of the data, wherein the set of tags includes the first tag and the second tag ([0023-0026], Golov teaches a mapping of tags to all allocated memory regions, which would include a case where it is done when the region size is not less than the size of the data to be stored on it. The region IDs are also associated with all allocated memory regions.)
While Golov the system of mapping logical addresses to tags, Golov/Kanno does not appear to explicitly disclose determining whether the first predefined size is less than a size of the data; responsive to determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data… and determining whether a sum of the first predefined size and the second predefined size is less than the size of the data.
However, Jiang teaches determining whether the first predefined size is less than a size of the data; responsive to determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data ([0044-0046], Jiang teaches a system which expands an allocated memory space by predetermined increments (sending a second portion of the data to be stored in a second memory section) when there are write requests to that memory space such that the total size of the memory to be stored is greater than the size of the memory space (the first predefined size is less than the size of data).).
Jiang further teaches determining whether a sum of the first predefined size and the second predefined size is less than the size of the data. (In [0043], since the process of Jiang [0044-0046] is done as needed to continue storing the data, another determining whether the data to be stored is greater than the memory size (determining whether the sum of all predefined sizes is less than the size of the data) is interpreted to be an obvious extension of the teachings of Jiang.)
Golov/Kanno and Jiang are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov/Kanno and Jiang to achieve the combined result of the system which dynamically assigns more memory portions to store new data into whenever the previous assignment is not enough, including in a case with a first and second memory portion (to store first and second portions of data) with first and second predefined sizes, and to determine whether the sum of the memory regions is less than the size of the data.
One of ordinary skill in the art would have been motivated to make this modification in order to adaptively increase the size of allocations to encompass larger amounts of storage as needed as discussed in Jiang [0032].
Regarding claim 3: The combination of Golov, Kanno, and Jiang teaches all limitations of claim 2, from which claim 3 depends.
Golov/Kanno/Jiang further teaches the first predefined size equals the second predefined size ([0022], Golov teaches that all sizes of the memory regions may be constant, ie. a first size equaling a second size).
Regarding claim 11: The combination of Golov and Kanno teaches all limitations of claim 10, from which claim 11 depends.
Golov/Kanno further teaches sending, to the controller of the memory device, a first portion of the data, wherein a first memory section of the plurality of memory sections stores the first portion of the data ([0024-0027], Golov teaches the processing of write commands to store data into allocated memory regions)
Golov/Kanno further teaches wherein the first portion of the data is in a first predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov/Kanno further teaches wherein the second memory section is associated with a second tag ([0023] and [0038], Golov teaches the mapping of memory regions to region IDs, and specifically that there are assigned region IDs for regions that are not even allocated yet, thereby rendering obvious a second memory section with a second tag.)
Golov/Kanno further teaches wherein the second portion of the data is in a second predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov/Kanno further teaches wherein mapping the tags to the logical addresses of the data is performed responsive to determining that the sum of the first predefined size and the second predefined size is not less than the size of the data, wherein the set of tags includes the first tag and the second tag ([0023-0026], Golov teaches a mapping of tags to all allocated memory regions, which would include a case where it is done when the region size is not less than the size of the data to be stored on it. The region IDs are also associated with all allocated memory regions.)
While Golov the system of mapping logical addresses to tags, Golov/Kanno does not appear to explicitly disclose determining whether the first predefined size is less than a size of the data; responsive to determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data… and determining whether a sum of the first predefined size and the second predefined size is less than the size of the data.
However, Jiang teaches determining whether the first predefined size is less than a size of the data; responsive to determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data ([0044-0046], Jiang teaches a system which expands an allocated memory space by predetermined increments (sending a second portion of the data to be stored in a second memory section) when there are write requests to that memory space such that the total size of the memory to be stored is greater than the size of the memory space (the first predefined size is less than the size of data).).
Jiang further teaches determining whether a sum of the first predefined size and the second predefined size is less than the size of the data. (In [0043], since the process of Jiang [0044-0046] is done as needed to continue storing the data, another determining whether the data to be stored is greater than the memory size (determining whether the sum of all predefined sizes is less than the size of the data) is interpreted to be an obvious extension of the teachings of Jiang.)
Golov/Kanno and Jiang are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov/Kanno and Jiang to achieve the combined result of the system which dynamically assigns more memory portions to store new data into whenever the previous assignment is not enough, including in a case with a first and second memory portion (to store first and second portions of data) with first and second predefined sizes, and to determine whether the sum of the memory regions is less than the size of the data.
One of ordinary skill in the art would have been motivated to make this modification in order to adaptively increase the size of allocations to encompass larger amounts of storage as needed as discussed in Jiang [0032].
Regarding claim 12: The combination of Golov, Kanno, and Jiang teaches all limitations of claim 11, from which claim 12 depends.
Golov/Kanno/Jiang further teaches the first predefined size equals the second predefined size ([0022], Golov teaches that all sizes of the memory regions may be constant, ie. a first size equaling a second size).
Regarding claim 17: The combination of Golov and Kanno teaches all limitations of claim 16, from which claim 17 depends.
Golov/Kanno further teaches sending, to the controller of the memory device, a first portion of the data, wherein a first memory section of the plurality of memory sections stores the first portion of the data ([0024-0027], Golov teaches the processing of write commands to store data into allocated memory regions)
Golov/Kanno further teaches wherein the first portion of the data is in a first predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov/Kanno further teaches wherein the second memory section is associated with a second tag ([0023] and [0038], Golov teaches the mapping of memory regions to region IDs, and specifically that there are assigned region IDs for regions that are not even allocated yet, thereby rendering obvious a second memory section with a second tag.)
Golov/Kanno further teaches wherein the second portion of the data is in a second predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov/Kanno further teaches wherein mapping the tags to the logical addresses of the data is performed responsive to determining that the sum of the first predefined size and the second predefined size is not less than the size of the data, wherein the set of tags includes the first tag and the second tag ([0023-0026], Golov teaches a mapping of tags to all allocated memory regions, which would include a case where it is done when the region size is not less than the size of the data to be stored on it. The region IDs are also associated with all allocated memory regions.)
While Golov the system of mapping logical addresses to tags, Golov/Kanno does not appear to explicitly disclose determining whether the first predefined size is less than a size of the data; responsive to determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data… and determining whether a sum of the first predefined size and the second predefined size is less than the size of the data.
However, Jiang teaches determining whether the first predefined size is less than a size of the data; responsive to determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data ([0044-0046], Jiang teaches a system which expands an allocated memory space by predetermined increments (sending a second portion of the data to be stored in a second memory section) when there are write requests to that memory space such that the total size of the memory to be stored is greater than the size of the memory space (the first predefined size is less than the size of data).).
Jiang further teaches determining whether a sum of the first predefined size and the second predefined size is less than the size of the data. (In [0043], since the process of Jiang [0044-0046] is done as needed to continue storing the data, another determining whether the data to be stored is greater than the memory size (determining whether the sum of all predefined sizes is less than the size of the data) is interpreted to be an obvious extension of the teachings of Jiang.)
Golov/Kanno and Jiang are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov/Kanno and Jiang to achieve the combined result of the system which dynamically assigns more memory portions to store new data into whenever the previous assignment is not enough, including in a case with a first and second memory portion (to store first and second portions of data) with first and second predefined sizes, and to determine whether the sum of the memory regions is less than the size of the data.
One of ordinary skill in the art would have been motivated to make this modification in order to adaptively increase the size of allocations to encompass larger amounts of storage as needed as discussed in Jiang [0032].
Regarding claim 18: The combination of Golov, Kanno, and Jiang teaches all limitations of claim 17, from which claim 18 depends.
Golov/Kanno/Jiang further teaches the first predefined size equals the second predefined size ([0022], Golov teaches that all sizes of the memory regions may be constant, ie. a first size equaling a second size).
Claims 6, 15 are rejected under 35 U.S.C. 103 as being unpatentable over
Golov, U.S. Pub. No. 20220129394 (hereinafter “Golov”) in view of
KANNO, U.S. Pub. No. 20170262228 (hereinafter “Kanno”) further in view of
Choi et al., U.S. Patent No. 12287968 (hereinafter “Choi”)
Regarding claim 6: The combination of Golov and Kanno teaches all limitations of claim 1, from which claim 6 depends.
Golov/Kanno does not appear to explicitly disclose the memory device is a compute express link (CXL) enabled memory device
However, Choi teaches the memory device is a compute express link (CXL) enabled memory device (Col. 6 line 56 to Col. 7 line 57, Choi teaches a system which uses a CXL protocol in order to implement a memory pooling and allocation scheme).
Golov/Kanno and Choi are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov/Kanno and Choi to achieve the combined result of the system which tags and maps memory portions, to do so on a CXL enabled device.
One of ordinary skill in the art would have been motivated to make this modification in order to implement a specific known technology that provides the protocols and architecture for memory pooling for multiple memories and hosts as discussed in Choi Col. 9 lines 1-45.
Regarding claim 15: The combination of Golov and Kanno teaches all limitations of claim 10, from which claim 15 depends.
Golov/Kanno does not appear to explicitly disclose the memory device is a compute express link (CXL) enabled memory device
However, Choi teaches the memory device is a compute express link (CXL) enabled memory device (Col. 6 line 56 to Col. 7 line 57, Choi teaches a system which uses a CXL protocol in order to implement a memory pooling and allocation scheme).
Golov/Kanno and Choi are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov/Kanno and Choi to achieve the combined result of the system which tags and maps memory portions, to do so on a CXL enabled device.
One of ordinary skill in the art would have been motivated to make this modification in order to implement a specific known technology that provides the protocols and architecture for memory pooling for multiple memories and hosts as discussed in Choi Col. 9 lines 1-45.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
HASHIMOTO, U.S. Pub. No. 20180107391, teaches a system in which a host operating system controls command routing and mapping file IDs of data to respective physical addresses, and receives responses including command IDs and physical addresses to track completion.
Wang et al., U.S. Pub. No. 20140195571, teaches a file system of a system maintains the mapping table to determine whether new writes are for a particular file.
Obr, U.S. Patent No. 9645752, teaches a system which controls writes from an application to a storage system, in which various host-side components perform write requests while attaching IDs of data items to be written and IDs to the write requests, in which the memory controller notifies the host when each data item is fully committed.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
