DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to submission of application on 19-MAY-2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action.
Claim Objections
Claims 2, 11, 17 are objected to because of the following informalities:
In claim 2, line 8, “responsive determining” should read “responsive to determining”.
In claim 11, line 8, “responsive determining” should read “responsive to determining”.
In claim 17, line 8, “responsive determining” should read “responsive to determining”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-10, 13-14, 16, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Golov, U.S. Pub. No. 20220129394 (hereinafter “Golov”).
Regarding claim 1: Golov teaches A host system comprising:
A memory; and a processing device, operatively coupled with the memory, to perform operations comprising: ([0015-0016], Golov teaches a system with a memory and host processor as an example physical embodiment.).
Sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections ([0019-0022], Golov teaches that a memory controller may receive a request to write data to the memory array from a host processor, and that the memory may include a plurality of regions (memory sections) defined as ranges of addresses in the memory array. Further, in [0068], Golov teaches that a memory array may be composed of a number of banks.)
Receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data. ([0022-0024] and [0042-0043], Golov teaches that the system of Golov can query a memory device to read a list of region IDs (tag information, comprising a set of tags in an order), with each region ID corresponding to a region which has its own logical addresses.)
Accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of tags ([0023-0025], Golov teaches that memory accesses reference a configuration table that stores a mapping of region identifiers to physical address ranges (aggregated DPA ranges, each associated with a tag, used to access data))
Regarding claim 4: Golov teaches all limitations of claim 1, from which claim 4 depends.
Golov further teaches each tag of the tags is unique (Golov Claim 6, Golov explicitly describes mappings being done to a plurality of unique corresponding region identifiers. Further, in Fig. 1 and [0022-0024], the listed regions are described following an ascending pattern, with each entry having its own ID).
Regarding claim 5: Golov teaches all limitations of claim 1, from which claim 5 depends.
Golov further teaches a size of each memory section allocated to the host system and associated with a respective tag is immutable (As described with respect to claim 1 and in [0038], Golov teaches memory regions (memory section) with region IDs (tags) mapped to VMs (host). Further, in [0022], Golov teaches that the size of the regions may be a constant size.)
Regarding claim 7: Golov teaches all limitations of claim 1, from which claim 7 depends.
Golov further teaches storing, in a host mapping data structure, the tags and the logical addresses ([0023-0028], Golov teaches that there may be mapping logic for the controllers which describe logical addresses to physical address mappings and region IDs.)
Regarding claim 8: Golov teaches all limitations of claim 1, from which claim 8 depends.
Golov further teaches generating an aggregation identifier that collectively identifies the tags associated with the data ([0037], Golov teaches maintaining a VM configuration table which maps VM identifiers (aggregation identifiers) to region IDs (tags associated with the data) that the VMs are mapped to.)
Regarding claim 9: Golov teaches all limitations of claim 1, from which claim 9 depends.
Golov further teaches storing, in a host mapping data structure, the tags, the logical addresses, and the aggregation identifier (Figs. 1 and 2, [0023-0028], and [0037], Golov teaches various information that the host processor maintains for mappings, which describes logical address to physical address mappings, region ID mappings, and VM identifier mappings.)
Regarding claim 10: Golov teaches A method comprising:
Sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections ([0019-0022], Golov teaches that a memory controller may receive a request to write data to the memory array from a host processor, and that the memory may include a plurality of regions (memory sections) defined as ranges of addresses in the memory array. Further, in [0068], Golov teaches that a memory array may be composed of a number of banks.)
Receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data. ([0022-0024] and [0042-0043], Golov teaches that the system of Golov can query a memory device to read a list of region IDs (tag information, comprising a set of tags in an order), with each region ID corresponding to a region which has its own logical addresses.)
Accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of tags ([0023-0025], Golov teaches that memory accesses reference a configuration table that stores a mapping of region identifiers to physical address ranges (aggregated DPA ranges, each associated with a tag, used to access data))
Regarding claim 13: Golov teaches all limitations of claim 10, from which claim 13 depends.
Golov further teaches each tag of the tags is unique (Golov Claim 6, Golov explicitly describes mappings being done to a plurality of unique corresponding region identifiers. Further, in Fig. 1 and [0022-0024], the listed regions are described following an ascending pattern, with each entry having its own ID).
Regarding claim 14: Golov teaches all limitations of claim 10, from which claim 14 depends.
Golov further teaches a size of each memory section allocated to the host system and associated with a respective tag is immutable (As described with respect to claim 10 and in [0038], Golov teaches memory regions (memory section) with region IDs (tags) mapped to VMs (host). Further, in [0022], Golov teaches that the size of the regions may be a constant size.)
Regarding claim 16: Golov teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: ([0091-0094], Golov teaches an example embodiment of the invention of Golov which is a non-transitory machine readable medium with information to be executed by a computing device to perform the various methods.).
Sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections ([0019-0022], Golov teaches that a memory controller may receive a request to write data to the memory array from a host processor, and that the memory may include a plurality of regions (memory sections) defined as ranges of addresses in the memory array. Further, in [0068], Golov teaches that a memory array may be composed of a number of banks.)
Receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data. ([0022-0024] and [0042-0043], Golov teaches that the system of Golov can query a memory device to read a list of region IDs (tag information, comprising a set of tags in an order), with each region ID corresponding to a region which has its own logical addresses.)
Accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of tags ([0023-0025], Golov teaches that memory accesses reference a configuration table that stores a mapping of region identifiers to physical address ranges (aggregated DPA ranges, each associated with a tag, used to access data))
Regarding claim 19: Golov teaches all limitations of claim 16, from which claim 19 depends.
Golov further teaches each tag of the tags is unique (Golov Claim 6, Golov explicitly describes mappings being done to a plurality of unique corresponding region identifiers. Further, in Fig. 1 and [0022-0024], the listed regions are described following an ascending pattern, with each entry having its own ID).
Regarding claim 20: Golov teaches all limitations of claim 16, from which claim 20 depends.
Golov further teaches a size of each memory section allocated to the host system and associated with a respective tag is immutable (As described with respect to claim 16 and in [0038], Golov teaches memory regions (memory section) with region IDs (tags) mapped to VMs (host). Further, in [0022], Golov teaches that the size of the regions may be a constant size.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 11-12, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over
Golov, U.S. Pub. No. 20220129394 (hereinafter “Golov”) in view of
Jiang et al., U.S. Pub. No. 20230152994 (hereinafter “Jiang”).
Regarding claim 2: Golov teaches all limitations of claim 1, from which claim 2 depends.
Golov further teaches sending, to the memory device, a first portion of the data, wherein a first memory section of the plurality of memory sections stores the first portion of the data ([0024-0027], Golov teaches the processing of write commands to store data into allocated memory regions)
Golov further teaches wherein the first portion of the data is in a first predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov further teaches wherein the second memory section is associated with a second tag ([0023] and [0038], Golov teaches the mapping of memory regions to region IDs, and specifically that there are assigned region IDs for regions that are not even allocated yet, thereby rendering obvious a second memory section with a second tag.)
Golov further teaches wherein the second portion of the data is in a second predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov further teaches wherein mapping the tags to the logical addresses of the data is performed responsive to determining that the sum of the first predefined size and the second predefined size is not less than the size of the data, wherein the set of tags includes the first tag and the second tag ([0023-0026], Golov teaches a mapping of tags to all allocated memory regions, which would include a case where it is done when the region size is not less than the size of the data to be stored on it. The region IDs are also associated with all allocated memory regions.)
While Golov the system of mapping logical addresses to tags, Golov does not appear to explicitly disclose determining whether the first predefined size is less than a size of the data; responsive determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data… and determining whether a sum of the first predefined size and the second predefined size is less than the size of the data.
However, Jiang teaches determining whether the first predefined size is less than a size of the data; responsive determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data ([0044-0046], Jiang teaches a system which expands an allocated memory space by predetermined increments (sending a second portion of the data to be stored in a second memory section) when there are write requests to that memory space such that the total size of the memory to be stored is greater than the size of the memory space (the first predefined size is less than the size of data).).
Jiang further teaches determining whether a sum of the first predefined size and the second predefined size is less than the size of the data. (In [0043], since the process of Jiang [0044-0046] is done as needed to continue storing the data, another determining whether the data to be stored is greater than the memory size (determining whether the sum of all predefined sizes is less than the size of the data) is interpreted to be an obvious extension of the teachings of Jiang.)
Golov and Jiang are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Jiang to achieve the combined result of the system which dynamically assigns more memory portions to store new data into whenever the previous assignment is not enough, including in a case with a first and second memory portion (to store first and second portions of data) with first and second predefined sizes, and to determine whether the sum of the memory regions is less than the size of the data.
One of ordinary skill in the art would have been motivated to make this modification in order to adaptively increase the size of allocations to encompass larger amounts of storage as needed as discussed in Jiang [0032].
Regarding claim 3: The combination of Golov and Jiang teaches all limitations of claim 2, from which claim 3 depends.
Golov/Jiang further teaches the first predefined size equals the second predefined size ([0022], Golov teaches that all sizes of the memory regions may be constant, ie. a first size equaling a second size).
Regarding claim 11: Golov teaches all limitations of claim 10, from which claim 11 depends.
Golov further teaches sending, to the memory device, a first portion of the data, wherein a first memory section of the plurality of memory sections stores the first portion of the data ([0024-0027], Golov teaches the processing of write commands to store data into allocated memory regions)
Golov further teaches wherein the first portion of the data is in a first predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov further teaches wherein the second memory section is associated with a second tag ([0023] and [0038], Golov teaches the mapping of memory regions to region IDs, and specifically that there are assigned region IDs for regions that are not even allocated yet, thereby rendering obvious a second memory section with a second tag.)
Golov further teaches wherein the second portion of the data is in a second predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov further teaches wherein mapping the tags to the logical addresses of the data is performed responsive to determining that the sum of the first predefined size and the second predefined size is not less than the size of the data, wherein the set of tags includes the first tag and the second tag ([0023-0026], Golov teaches a mapping of tags to all allocated memory regions, which would include a case where it is done when the region size is not less than the size of the data to be stored on it. The region IDs are also associated with all allocated memory regions.)
While Golov the system of mapping logical addresses to tags, Golov does not appear to explicitly disclose determining whether the first predefined size is less than a size of the data; responsive determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data… and determining whether a sum of the first predefined size and the second predefined size is less than the size of the data.
However, Jiang teaches determining whether the first predefined size is less than a size of the data; responsive determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data ([0044-0046], Jiang teaches a system which expands an allocated memory space by predetermined increments (sending a second portion of the data to be stored in a second memory section) when there are write requests to that memory space such that the total size of the memory to be stored is greater than the size of the memory space (the first predefined size is less than the size of data).).
Jiang further teaches determining whether a sum of the first predefined size and the second predefined size is less than the size of the data. (In [0043], since the process of Jiang [0044-0046] is done as needed to continue storing the data, another determining whether the data to be stored is greater than the memory size (determining whether the sum of all predefined sizes is less than the size of the data) is interpreted to be an obvious extension of the teachings of Jiang.)
Golov and Jiang are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Jiang to achieve the combined result of the system which dynamically assigns more memory portions to store new data into whenever the previous assignment is not enough, including in a case with a first and second memory portion (to store first and second portions of data) with first and second predefined sizes, and to determine whether the sum of the memory regions is less than the size of the data.
One of ordinary skill in the art would have been motivated to make this modification in order to adaptively increase the size of allocations to encompass larger amounts of storage as needed as discussed in Jiang [0032].
Regarding claim 12: The combination of Golov and Jiang teaches all limitations of claim 11, from which claim 12 depends.
Golov/Jiang further teaches the first predefined size equals the second predefined size ([0022], Golov teaches that all sizes of the memory regions may be constant, ie. a first size equaling a second size).
Regarding claim 17: Golov teaches all limitations of claim 16, from which claim 17 depends.
Golov further teaches sending, to the memory device, a first portion of the data, wherein a first memory section of the plurality of memory sections stores the first portion of the data ([0024-0027], Golov teaches the processing of write commands to store data into allocated memory regions)
Golov further teaches wherein the first portion of the data is in a first predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov further teaches wherein the second memory section is associated with a second tag ([0023] and [0038], Golov teaches the mapping of memory regions to region IDs, and specifically that there are assigned region IDs for regions that are not even allocated yet, thereby rendering obvious a second memory section with a second tag.)
Golov further teaches wherein the second portion of the data is in a second predefined size ([0022], Golov teaches that the sizes of the given regions are a constant size.)
Golov further teaches wherein mapping the tags to the logical addresses of the data is performed responsive to determining that the sum of the first predefined size and the second predefined size is not less than the size of the data, wherein the set of tags includes the first tag and the second tag ([0023-0026], Golov teaches a mapping of tags to all allocated memory regions, which would include a case where it is done when the region size is not less than the size of the data to be stored on it. The region IDs are also associated with all allocated memory regions.)
While Golov the system of mapping logical addresses to tags, Golov does not appear to explicitly disclose determining whether the first predefined size is less than a size of the data; responsive determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data… and determining whether a sum of the first predefined size and the second predefined size is less than the size of the data.
However, Jiang teaches determining whether the first predefined size is less than a size of the data; responsive determining that the first predefined size is less than the size of the data, sending, to the memory device, a second portion of the data, wherein a second memory section of the plurality of memory sections stores the second portion of the data ([0044-0046], Jiang teaches a system which expands an allocated memory space by predetermined increments (sending a second portion of the data to be stored in a second memory section) when there are write requests to that memory space such that the total size of the memory to be stored is greater than the size of the memory space (the first predefined size is less than the size of data).).
Jiang further teaches determining whether a sum of the first predefined size and the second predefined size is less than the size of the data. (In [0043], since the process of Jiang [0044-0046] is done as needed to continue storing the data, another determining whether the data to be stored is greater than the memory size (determining whether the sum of all predefined sizes is less than the size of the data) is interpreted to be an obvious extension of the teachings of Jiang.)
Golov and Jiang are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Jiang to achieve the combined result of the system which dynamically assigns more memory portions to store new data into whenever the previous assignment is not enough, including in a case with a first and second memory portion (to store first and second portions of data) with first and second predefined sizes, and to determine whether the sum of the memory regions is less than the size of the data.
One of ordinary skill in the art would have been motivated to make this modification in order to adaptively increase the size of allocations to encompass larger amounts of storage as needed as discussed in Jiang [0032].
Regarding claim 18: The combination of Golov and Jiang teaches all limitations of claim 17, from which claim 18 depends.
Golov/Jiang further teaches the first predefined size equals the second predefined size ([0022], Golov teaches that all sizes of the memory regions may be constant, ie. a first size equaling a second size).
Claims 6, 15 are rejected under 35 U.S.C. 103 as being unpatentable over
Golov, U.S. Pub. No. 20220129394 (hereinafter “Golov”) in view of
Choi et al., U.S. Patent No. 12287968 (hereinafter “Choi”)
Regarding claim 6: Golov teaches all limitations of claim 1, from which claim 6 depends.
Golov does not appear to explicitly disclose the memory device is a compute express link (CXL) enabled memory device
However, Choi teaches the memory device is a compute express link (CXL) enabled memory device (Col. 6 line 56 to Col. 7 line 57, Choi teaches a system which uses a CXL protocol in order to implement a memory pooling and allocation scheme).
Golov and Choi are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Choi to achieve the combined result of the system which tags and maps memory portions, to do so on a CXL enabled device.
One of ordinary skill in the art would have been motivated to make this modification in order to implement a specific known technology that provides the protocols and architecture for memory pooling for multiple memories and hosts as discussed in Choi Col. 9 lines 1-45.
Regarding claim 15: Golov teaches all limitations of claim 10, from which claim 15 depends.
Golov does not appear to explicitly disclose the memory device is a compute express link (CXL) enabled memory device
However, Choi teaches the memory device is a compute express link (CXL) enabled memory device (Col. 6 line 56 to Col. 7 line 57, Choi teaches a system which uses a CXL protocol in order to implement a memory pooling and allocation scheme).
Golov and Choi are analogous art because they are from the same field of endeavor, memory management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Golov and Choi to achieve the combined result of the system which tags and maps memory portions, to do so on a CXL enabled device.
One of ordinary skill in the art would have been motivated to make this modification in order to implement a specific known technology that provides the protocols and architecture for memory pooling for multiple memories and hosts as discussed in Choi Col. 9 lines 1-45.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gucea et al., U.S. Pub. No. 20220035434, teaches a system which allocates more memory banks when the current allocated region size is not enough for executing operations.
Stabrawa et al., U.S. Pub. No. 20230008874, teaches a system which adds more memory to an allocation when receiving accesses from outside of a known space.
Guda et al., U.S. Pub. No. 20210255949, teaches a system of using zones with given IDs to store data.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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