DETAILED ACTION
The instant application having Application No. 19/212,220 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/212,220 filed 5/19/2025 is a Continuation of 18/137,820 filed 4/21/2023, now U.S. Patent #12321594.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/30/2025 is being considered by the examiner.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
For instances of abbreviated terms NAND and XOR, the examiner recommends providing the full intended terminology for the initial uses of the terms by, for example, specifying NAND memory as NAND (NOT AND) memory and XOR operation as XOR (Exclusive-OR) operation.
For claim 5 reciting, “recovering the corrupted portion by performing a parity operation on the compressed parity value, all uncorrupted portions of the received data item; and all portions of all other data items in the compressed parity data item group including the second parity value;” the examiner recommends amending the limitation to state, “recovering the corrupted portion by performing a parity operation on the compressed parity value, all uncorrupted portions of the received data item[[;]], and all portions of all other data items in the compressed parity data item group including the second parity value;”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-3, 9-11, and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 8, 12, 15, and 19 of U.S. Patent No. 12321594. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application.
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Instant application 19/212,220
U.S. Patent #12321594 (corresponding to Application # 18/137,820)
1. A NAND memory device comprising:
an array of NAND memory cells organized into multiple planes and addressable by multiple page lines; and
a controller configured to perform operations comprising:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
2. The NAND memory device of claim 1, wherein calculating the first parity value comprises applying an XOR operation to the first portion, second portion, and third portion of the received data item.
1. A NAND memory device comprising:
an NAND array of NAND memory cells organized into multiple planes and addressable by multiple page lines; and
a controller configured to perform operations comprising:
storing a received data item in memory cells of the NAND array such that a first portion, a second portion and a third portion of the received data item are stored in memory cells in the NAND array such that the first portion, the second portion, and the third portion are on different page lines with respect to each other;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item stored in second memory cells in the NAND array on different page lines and different planes with respect to each other; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
3. The NAND memory device of claim 1, wherein calculating the compressed parity value comprises applying an XOR operation to the first parity value and the second parity value.
5. The NAND memory device of claim 1, wherein the operations of calculating the compressed parity value comprises XORing the first parity value and the second parity value.
9. A method for managing data in a NAND memory device, the method comprising: using one or more computer processors:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
10. The method of claim 9, wherein the method further comprises: applying an XOR operation to the first portion, second portion, and third portion of the received data item to calculate the first parity value.
8. A method comprising:
storing a received data item in memory cells of a NAND array such that a first portion, a second portion and a third portion of the received data item are stored in memory cells in the NAND array such that the first portion, the second portion, and the third portion are on different page lines with respect to each other;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item stored in second memory cells in the NAND array on different page lines and different planes with respect to each other; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
11. The method of claim 9, wherein the method further comprises: applying an XOR operation to the first parity value and the second parity value to calculate the compressed parity value.
12. The method of claim 8, wherein calculating the compressed parity value comprises XORing the first parity value and the second parity value.
17. A non-transitory machine-readable medium, storing instructions for managing data in a NAND memory device, the instructions, which when executed, cause a machine to perform operations comprising:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein the operation of programming each data portion of the received data item further comprises programming each portion on a different page line than every other data portion;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
18. The non-transitory machine-readable medium of claim 17, wherein the operation of calculating the first parity value further comprises applying an XOR operation to the first portion, second portion, and third portion of the received data item.
15. A non-transitory, machine-readable medium, storing instructions, which when executed, cause a machine to perform operations comprising:
storing a received data item in memory cells of a NAND array such that a first portion, a second portion and a third portion of the received data item are stored in memory cells in the NAND array such that the first portion, the second portion, and the third portion are on different page lines with respect to each other;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item stored in second memory cells in the NAND array on different page lines and different planes with respect to each other; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
19. The non-transitory machine-readable medium of claim 17, wherein the operation of calculating the compressed parity value further comprises applying an XOR operation to the first parity value and the second parity value.
19. The non-transitory, machine-readable medium of claim 15, wherein the operations of calculating the compressed parity value comprises XORing the first parity value and the second parity value.
Regarding claims 1-2, 9-10, and 17-18, U.S. Patent #12321594 discloses all limitations except organizing data portions diagonally into the first, second, and third pages of respective first, second, and third dies, each data portion programmed on a different page line than every other data portion, and calculating first parity value by applying XOR operation to the first, second, and third portion. However, Kang et al. (US 20180129430 A1) teaches a stripe including data pages diagonally striped across at least three dies so that every other page is on a different page line (para. 62; fig. 7A and associated paragraphs; see, for example, on fig. 7A, pages D2 on plane 0 of die 0, die 1, and die 2 being on a different page line than every other pages D2 on plane 1 of die 0, die 1, and die 2) and further teaches parity generated by bitwise XOR of data pages in a stripe (para. 56).
U.S. Patent #12321594 and Kang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12321594 and Kang, to modify the disclosures by U.S. Patent #12321594 to include disclosures by Kang since they both teach data storage and error correction, wherein Kang is directed towards improved error correcting codes and processes for overcoming read errors (para. 4). Therefore, it would be applying a known technique (a stripe including data pages diagonally striped across multiples dies so that every other data page is on a different page line, performing XORing of data pages in the stripe to generate parity) to a known device (memory device storing received first, second, and third data portions on different page lines with respect to each other, calculating a first parity value using received data portions) ready for improvement to yield predictable results (memory device storing received first, second, and third data portions diagonally across multiples dies so that every other data portion is on a different page line, calculating a first parity value for received data portions by performing XORing of the received data portions, as doing so would provide for greater flexibility in striping arrangement of data items). MPEP 2143
The double patenting rejection above applies to claims 1-2, 9-10, and 17-18.
Claims 1-3, 9-11, and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 8, 12, 15, and 19 of U.S. Patent No. 11635894. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application.
Instant application 19/212,220
U.S. Patent #11635894 (corresponding to Application #16/488,696)
1. A NAND memory device comprising:
an array of NAND memory cells organized into multiple planes and addressable by multiple page lines; and
a controller configured to perform operations comprising:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
1. A NAND memory device comprising:
an array of NAND memory cells organized into multiple planes and addressable by multiple page lines; and
a controller configured to perform operations comprising:
programming a received data item into a first data stripe by programming a first portion of the received data item into a first page line of the multiple page lines on a first plane of the multiple planes, a second portion of the received data item into a second page line of the multiple page lines on a second plane of the multiple planes, and a third portion of the received data item into a third page line of the multiple page lines on a third plane of the multiple planes, wherein a third page number of the third page line is greater than a second page number of the second page line and a third plane number of the third plane is greater than a second plane number of the second plane, and wherein a second page number of the second page line is greater than a first page number of the first page line and a second plane number of the second plane is greater than a first plane number of a first plane;
calculating a parity value for the received data item using the first portion, second portion, and third portion;
storing the parity value with multiple other parity values in a first parity cluster of multiple parity clusters, each particular one of the other parity values storing a parity value for a different stripe, the parity values stored in the multiple page lines and the multiple planes;
compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of a parity cluster within the multiple parity clusters to create compressed parity values;
storing the compressed parity values in the array of NAND cells and
wherein the operations of storing the compressed parity values in the array of NAND cells comprises overwriting the multiple other parity values with the compressed parity values.
2. The NAND memory device of claim 1, wherein calculating the first parity value comprises applying an XOR operation to the first portion, second portion, and third portion of the received data item.
4. The NAND memory device of claim 1, wherein the operations of calculating the parity value for the received data item using the first portion, second portion, and third portion comprises applying an XOR operator to the first portion, second portion, and third portion.
3. The NAND memory device of claim 1, wherein calculating the compressed parity value comprises applying an XOR operation to the first parity value and the second parity value.
3. The NAND memory device of claim 1, wherein the operations of compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of the parity cluster within the multiple parity clusters to create compressed parity values comprises utilizing an XOR operation.
9. A method for managing data in a NAND memory device, the method comprising: using one or more computer processors:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
1. A NAND memory device comprising:
an array of NAND memory cells organized into multiple planes and addressable by multiple page lines; and
a controller configured to perform operations comprising:
programming a received data item into a first data stripe by programming a first portion of the received data item into a first page line of the multiple page lines on a first plane of the multiple planes, a second portion of the received data item into a second page line of the multiple page lines on a second plane of the multiple planes, and a third portion of the received data item into a third page line of the multiple page lines on a third plane of the multiple planes, wherein a third page number of the third page line is greater than a second page number of the second page line and a third plane number of the third plane is greater than a second plane number of the second plane, and wherein a second page number of the second page line is greater than a first page number of the first page line and a second plane number of the second plane is greater than a first plane number of a first plane;
calculating a parity value for the received data item using the first portion, second portion, and third portion;
storing the parity value with multiple other parity values in a first parity cluster of multiple parity clusters, each particular one of the other parity values storing a parity value for a different stripe, the parity values stored in the multiple page lines and the multiple planes;
compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of a parity cluster within the multiple parity clusters to create compressed parity values;
storing the compressed parity values in the array of NAND cells and
wherein the operations of storing the compressed parity values in the array of NAND cells comprises overwriting the multiple other parity values with the compressed parity values.
10. The method of claim 9, wherein the method further comprises: applying an XOR operation to the first portion, second portion, and third portion of the received data item to calculate the first parity value.
4. The NAND memory device of claim 1, wherein the operations of calculating the parity value for the received data item using the first portion, second portion, and third portion comprises applying an XOR operator to the first portion, second portion, and third portion.
11. The method of claim 9, wherein the method further comprises: applying an XOR operation to the first parity value and the second parity value to calculate the compressed parity value.
3. The NAND memory device of claim 1, wherein the operations of compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of the parity cluster within the multiple parity clusters to create compressed parity values comprises utilizing an XOR operation.
17. A non-transitory machine-readable medium, storing instructions for managing data in a NAND memory device, the instructions, which when executed, cause a machine to perform operations comprising:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein the operation of programming each data portion of the received data item further comprises programming each portion on a different page line than every other data portion;
calculating a first parity value for the received data item using the first portion, the second portion, and the third portion;
assigning the first parity value for the received data item into a first position of a first parity cluster;
calculating a compressed parity value using the first parity value and a second parity value of a second parity cluster, the second parity value occupying a same first position in the second parity cluster as the first parity value, the second parity value a parity value of a first, a second, and a third portion of a second data item; and
storing the compressed parity value in a portion of a NAND block that was used to store either the first or second parity value.
first portion, second portion, and third portion of the received data item.
8. A non-transitory machine-readable medium, comprising instructions, which when executed by a machine, cause the machine to perform operations comprising:
programming a received data item into a first data stripe by programming a first portion of the received data item into a first page line of multiple page lines on a first plane of multiple planes of a NAND array, a second portion of the received data item into a second page line of the multiple page lines on a second plane of the multiple planes, and a third portion of the received data item into a third page line of the multiple page lines on a third plane of the multiple planes, wherein a third page number of the third page line is greater than a second page number of the second page line and a third plane number of the third plane is greater than a second plane number of the second plane, and wherein a second page number of the second page line is greater than a first page number of the first page line and a second plane number of the second plane is greater than a first plane number of a first plane;
calculating a parity value for the received data item using the first portion, second portion, and third portion;
storing the parity value with multiple other parity values in a first parity cluster of multiple parity clusters, each particular one of the other parity values storing a parity value for a different stripe, the parity values stored in the multiple page lines and the multiple planes;
compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of a parity cluster within the multiple parity clusters to create compressed parity values;
storing the compressed parity values in the NAND array; and
wherein the operations of storing the compressed parity values in the array of NAND cells comprises overwriting the multiple other parity values with the compressed parity values.
18. The non-transitory machine-readable medium of claim 17, wherein the operation of calculating the first parity value further comprises applying an XOR operation to the
11. The non-transitory machine-readable medium of claim 8, wherein the operations of calculating the parity value for the received data item using the first portion, second portion, and third portion comprises applying an XOR operator to the first portion, second portion, and third portion.
19. The non-transitory machine-readable medium of claim 17, wherein the operation of calculating the compressed parity value further comprises applying an XOR operation to the first parity value and the second parity value.
10. The non-transitory machine-readable medium of claim 8, wherein the operations of compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of the parity cluster within the multiple parity clusters to create compressed parity values comprises utilizing an XOR operation.
Regarding claims 1, 9, and 17, U.S. Patent #11635894 discloses all limitations except organizing data portions diagonally into the first, second, and third pages of respective first, second, and third dies, each data portion programmed on a different page line than every other data portion. However, Kang et al. (US 20180129430 A1) teaches a stripe including data pages diagonally striped across at least three dies so that every other page is on a different page line (para. 62; fig. 7A and associated paragraphs; see, for example, on fig. 7A, pages D2 on plane 0 of die 0, die 1, and die 2 being on a different page line than every other pages D2 on plane 1 of die 0, die 1, and die 2).
U.S. Patent #11635894 and Kang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #11635894 and Kang, to modify the disclosures by U.S. Patent #11635894 to include disclosures by Kang since they both teach data storage and error correction, wherein Kang is directed towards improved error correcting codes and processes for overcoming read errors (para. 4). Therefore, it would be applying a known technique (a stripe including data pages diagonally striped across multiples dies so that every other data page is on a different page line, calculating parity value based on the data pages) to a known device (memory device storing received first, second, and third data portions on different page lines and planes with respect to each other, calculating a first parity value based on received data portions) ready for improvement to yield predictable results (memory device storing received first, second, and third data portions diagonally across multiples dies so that every other data portion is on a different page line, calculating a first parity value for received data portions, as doing so would provide for greater flexibility in striping arrangement of data items). MPEP 2143
The double patenting rejection above applies to claims 1-2, 9-10, and 17-18.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
B et al. (US 20160266965 A1) teaches, responsive to replacing a block of data used in generating an old XOR parity with a new block, calculating an updated XOR parity using the new block for overwriting the old XOR parity.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS KIM whose telephone number is (571)272-8093. The examiner can normally be reached Monday - Friday: 7:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JARED RUTZ can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
Prosecution Insights