Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of claims 1-11 and 19-25 in the reply filed on 6/9/2026 is acknowledged. Claims 12-18 have been cancelled, claims 26-32 are newly added, therefore, claims 1-11, 19-32 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-9, 11, 26-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US 2022/0083267 A1.
Regarding claims 1 and 26, Chen teaches a memory apparatus, comprising:
one or more controllers configured to:
operate, based on a first one or more values of one or more performance parameters (according to applicant’s specification section 0016; performance parameters such as the number of write commands, the data size in the command queue, and/or bandwidth utilization for write operations; Chen teaches the controller memory buffer size in section 0035), in a first write operation mode (claim 1 of Chen, step (a) &(b) and section 0035);
receive, from a host system and while operating in the first write operation mode, a command indicating that data is to be immediately written to a non-volatile memory location associated with the memory apparatus (claim 1; step (c));
refrain, based on operating in the first write operation mode, from writing the data to the non-volatile memory location (claim 1; step (d));
transmit, to the host system, an indication that the command has been completed while the data is stored in a temporary storage location (claim 1; step (e));
operate, after transmitting the indication that the command has been completed, in a second write operation mode (claim 1; step (f)); and
write, while operating in the second write operation mode, the data from the temporary storage location to the non-volatile memory location (claim 1; step (g)).
Regarding claims 2 and 27, Chen teaches the command is a write command indicating the data, and wherein the one or more controllers are further configured to store, based on operating in the first write operation mode, the data in the temporary storage location (section 0034; When there is a CMB 220 in the SSD 212, the write data can be pushed 222 directly into the CMB 220).
Regarding claims 4 and 28, Chen teaches the one or more controllers are further configured to: set a flag associated with the data stored in the temporary storage location, wherein the flag indicates that the data is associated with an immediate write indication (section 0043; The NAND channel controller 410 provides feedback information 420 to the datapath component 406 indicating that a NAND die scheduled to be programmed is ready for transfer. Upon receiving the feedback information 420, the datapath component 406 reads 422 the data 416 from the CMB 404 and starts the processing the data from the CMB 404 to obtain processed data 424 and transfers the processed data 424 to the NAND channel controller 410).
Regarding claims 5 and 29, Chen teaches the one or more controllers, to write the data from the temporary storage location to the non-volatile memory location (section 0042-0043), are configured to receive, from the host system and while operating in the second write operation mode, a write command; and write the data from the temporary storage location to the non-volatile memory location based on receiving the write command and based on the data being associated with the flag (Fig.4; the data and metadata 416 for the write command 414 reside in the CMB 404 in its raw format even after the controller 402 receives the write command 414. The LBA (logical block address) information 418 of the write command 414 is passed towards the NAND 408, going through the FTL 412 and other control path components as known in the art. The NAND channel controller 410 provides feedback information 420 to the datapath component 406 indicating that a NAND die scheduled to be programmed is ready for transfer. Upon receiving the feedback information 420, the datapath component 406 reads 422 the data 416 from the CMB 404 and starts the processing the data from the CMB 404 to obtain processed data 424 and transfers the processed data 424 to the NAND channel controller 410).
Regarding claims 6 and 30, Chen teaches the one or more controllers, to operate in the first write operation mode, are configured to: receive, from the host system, an indication that the first write operation mode is enabled for the memory apparatus; and operate in the first write operation mode based on receiving the indication that the first write operation mode is enabled (clam 1 and 2; the storage device is a NAND flash storage device and wherein the ready signal is received from a NAND channel controller coupled to the NAND flash storage device, the ready signal indicating that the NAND flash storage device is ready to be programmed).
Regarding claim 7, Chen teaches the one or more controllers, to operate in the second write operation mode, are configured to: receive, from the host system, an indication that the first write operation mode is disabled for the memory apparatus; and operate in the second write operation mode based on receiving the indication that the first write operation mode is disabled (section 0046; the data transfer from the host memory space is postponed since the host memory space is borrowed for the controller's write buffer. It means that host non-FUA write command completion also must be postponed. A non-FUA write command is the typical write command that a host sends and doesn't require the write data to reach the non-volatile media (NAND) before the controller sends back an acknowledgement of command completion. Typically, controllers send back the command completion once the data is written to the write buffer. In the above implementation, the controller is not able send back this “early” completion because the CMB is in the host memory space).
Regarding claims 8 and 31, Chen teaches the command includes a write command with a forced unit access indication indicating that the data is to be immediately written to the non-volatile memory location (section 0033; When the remote host application issues a write command towards a SSD 212 without CMB).
Regarding claim 9 and 32, Chen teaches the data in the temporary storage location, and wherein the command includes a synchronize cache command indicating the data in the temporary storage location is to be immediately written to the non-volatile memory location (section 0034; When there is a CMB 220 in the SSD 212, the write data can be pushed 222 directly into the CMB 220. When the SSD 212 receives a write command either from the device application or from a NVMeoF accelerator, the controller of the SSD 212 reads the data out from the CMB 220 and writes it to the NAND device).
Regarding claim 11, Chen teaches the one or more performance parameters include at least one of: a quantity of write commands in a command queue of the memory apparatus, a size of data associated with the write commands in the command queue, or a bandwidth utilization for write operations by the memory apparatus (section 0035; it is taught as the CMB size).
Allowable Subject Matter
Claims 19-25 are allowed.
Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include receive, from the host system, configuration information for the first write operation mode, wherein the configuration information indicates one or more thresholds, and wherein the one or more controllers, to operate in the first write operation mode, are configured to: detect that the first one or more values satisfy respective thresholds of the one or more thresholds; and operate in the first write operation mode based on the first one or more values satisfying the respective thresholds in combination with the other claimed limitations as described in the claim 3.
The limitations not found in the prior art of record include the one or more controllers, to operate in the first write operation mode, are configured to: operate in the first write operation mode based on the first one or more values satisfying one or more thresholds, and wherein the one or more controllers, to operate in the second write operation mode, are configured to: operate in the second write operation mode based on a second one or more values of the one or more performance parameters not satisfying the one or more thresholds in combination with the other claimed limitations as described in the claim 10.
The limitations not found in the prior art of record include detecting, by a memory apparatus, that a first one or more values of one or more performance parameters satisfy one or more thresholds; receiving, by the memory apparatus and from a host system and while the first one or more values of the one or more performance parameters satisfy the one or more thresholds, a command indicating that data is to be immediately written to a non-volatile memory location associated with the memory apparatus; storing, by the memory apparatus and based on the first one or more values satisfying the one or more thresholds, the data in a temporary storage location in combination with the other claimed limitations as described in the claim 19 (claims 20-25 are depended on claim 19).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NUMATA et al., US 2015/0071003 A1 teaches a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133
