DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Office acknowledges the amendment dated 02 June 2026, in which:
Claims 1-23 are currently pending.
Claims 1, 2, 4, 5, 7, 11-13, 16, 18-21, and 23 are amended.
Response to Arguments
Applicant’s arguments with respect to the 35 U.S.C. § 103 rejections of independent claims 1 and 23 have been fully considered. Applicant argues that the combination of Kim and Yang fails to teach or suggest the newly added limitations requiring the pixel driving circuit to include "a first partial circuit and a second partial circuit arranged opposite to each other in a second direction" with "at least two signal transmission lines being located between the first partial circuit and the second partial circuit." Applicant correctly notes that while Kim discloses the electrical schematic for splitting the PWM and PAM logic, Kim does not detail the physical spatial layout of these blocks on the substrate. Similarly, Applicant correctly notes that Yang teaches physical layout rules for mitigating capacitance at intersections but does not explicitly teach partitioning a single pixel circuit into two opposed blocks separated by intermediate signal lines.
Applicant's arguments are persuasive with respect to the combination of Kim and Yang alone. However, these arguments are overcome by the incorporation of Cheng et al. (US 2018/0108676, hereinafter "Cheng") into the base rejection.
Cheng expressly teaches the physical topography that Kim and Yang lack. Cheng discloses a pixel circuit wherein the driving components (e.g., thin film transistors and pixel electrodes) are physically partitioned and arranged on opposite sides of an intervening signal transmission line specifically to reduce mutual interference between the components (Cheng: Para. [0008], [0027], [0041], [0054], and Figs. 1A, 4). Cheng illustrates in Figure 1A and details in Paragraph [0027] that the components are respectively positioned at the two sides of the gate line 2 and are disposed to be opposite to each other. Furthermore, Cheng provides cross-sectional proof in Figure 4 and Paragraph [0041] demonstrating that the opposed elements are located in different sides of the gate line 2. Cheng also expressly states that this opposed arrangement is a deliberate manufacturing layout step (Cheng: Paragraph [0054]).
The requirement that “at least two signal transmission lines” are physically located between the first and second partial circuits is addressed through the obviousness combination of Kim as modified by Yang and Cheng, rather than a signal reference explicitly anticipating the entire phrase verbatim. Cheng provides the opposed physical layout and the intervening signal space. Kim provides the requirement for multiple (at least two) signal lines. Yang provides the multi-line routing rules. When a person having ordinary skill in the art applies Cheng’s opposed separation physical layout to Kim’s 13-transistor circuit, they must figure out where to route the massive number of signal lines Kim requires. A person having ordinary skill in the art would be motivated to take the functionally split PWM and PAM electrical circuits taught by Kim and physically arrange them opposite to each other across central signal transmission lines as taught by Cheng. Applying this opposed spatial layout to Kim's split circuits allows the high density of control lines to be efficiently routed down the center of the pixel without increasing the overall footprint, while applying Yang's intersection rules prevents the resulting dense central matrix from suffering from parasitic capacitance.
Allowable Subject Matter
Claims 19-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The objections and 35 U.S.C. § 112(b) rejections directed to Claims 1, 5, 4, 7, 11-13, 16, 18, 19 and 21 have been withdrawn in view of Applicant's amendments resolving the indefiniteness, antecedent basis, and grammatical issues.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2020/0312216, hereinafter "Kim") in view of Yang et al. (US 2022/0238630, hereinafter "Yang") and Cheng et al (US 2018/0108676, hereinafter "Cheng").
With respect to Claim 1 (Currently Amended), Kim teaches a display panel, comprising:
a pixel driving circuit, including a driving transistor and a first transistor, one terminal of the first transistor being connected to a gate of the driving transistor through a gate device connection line (Kim: Para. [0119], [0180], a PAM driving circuit 720 including driving transistor T8, and a PWM driving circuit 710 including first transistor T3 configured such that the PWM driving circuit controls the driving time of the current provided by the PAM driving circuit); and
a plurality of signal transmission lines providing control signals or input signals for the pixel driving circuit (Kim: Para. [0141], [0260], [0263], data lines that deliver input voltages to the driving circuits).
Kim fails to expressly disclose:
wherein a signal transmission line of the plurality of signal transmission lines extends in a first direction; the gate device connection line includes a first connection line portion extending in a second direction; and in a direction perpendicular to a plane where the display panel is located, the first connection line portion at least partially overlaps with at least two signal transmission lines, where the first direction intersects with the second direction.
However, Yang discloses:
a signal transmission line extending in a first direction, a connection line portion extending in a second direction, and in a direction perpendicular to a plane where the display panel is located, the connection line at least partially overlapping with the signal transmission lines, where the first direction intersects with the second direction (Yang: Para. [0205], an array substrate having a reset signal line extending along a first direction, a power line extending along a second direction, wherein the reset signal line has an overlapping region with the power line, and the first direction intersects with the second direction).
Therefore, it would be obvious to one of ordinary skill in the art to modify the display panel, as taught by Kim, to incorporate the intersecting orthogonal routing matrix layout, as taught by Yang, in order to properly route the high density of control and data signals to the multiple transistors within the microscopic footprint of the pixel circuit without increasing the overall pixel area (Yang: Para. [0209]).
Kim as modified by Yang fails to expressly disclose:
The physical spatial arrangement of partial circuit components arranged opposite to each other, with signal transmission lines routed physically between them
However, Cheng discloses:
The pixel driving circuit including a first partial circuit and a second partial circuit arranged opposite to each other in a second direction, the first transistor being located in the first partial circuit and the driving transistor being located in the second partial circuit (Cheng: Para. [0008], [0027], [0041], [0054], and Figs. 1A, 4, disclosing the physical layout and cross-sectional illustration of oppositely arranged partial circuits separated by signal lines to prevent interference); and the at least two signal transmission lines being located between the first partial circuit and the second partial circuit (Kim teaches a 13-transistor hybrid PWM and PAM pixel circuit. Unlike Cheng’s simple circuit, Kim’s design fundamentally requires a large number of signal transmission lines to independently drive the two partial circuits (PWM and PAM). Cheng teaches putting a signal line between the opposed circuits, while Kim and Yang make it obvious that for a complex hybrid display, that space must accommodate multiple (at least two) signal lines.).
Therefore, it would be obvious to one of ordinary skill in the art to modify the display panel, as taught by Kim and Yang, to physically arrange the partial circuits opposite to each other with signal lines located between them as taught by Cheng to reduce mutual interference (Cheng: Para. [0005]).
With respect to Claim 2 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 1, comprising:
a substrate, wherein the pixel driving circuit is located on the substrate; the pixel driving circuit includes a first partial circuit and a second partial circuit arranged opposite to each other (Kim: Para. [0087], [0109], substrate 30, a first pixel circuit for PWM driving and a second pixel circuit for PAM driving); and a plurality of signal transmission lines located between the partial circuits (Yang: Para. [0275], Fig. 16, routing signal lines such as initialization and power lines between circuit units).
With respect to Claim 3, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 2, wherein the first partial circuit comprises a first capacitor, and the second partial circuit includes a second capacitor (Kim: Para. [0146], PWM pixel circuit implemented with thirteen transistors and two capacitors C1 and C2).
With respect to Claim 4 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 3, wherein at an overlapping area of the transistor in the first partial circuit and the signal transmission line, a gate of a transistor multiplexes a portion of a line segment of a corresponding intermediate signal transmission line (Yang: Para. [0274], the reset signal line overlaps the seventh channel region to form the seventh thin film transistor, demonstrating the integral multiplexing of a signal line segment as a transistor gate).
With respect to Claim 5 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 2, wherein the plurality of signal transmission lines also include at least one first edge signal transmission line located at a side of the first partial circuit away from the second partial circuit (Yang: Para. [0274], arranging transmission lines such as gate lines and data lines along the peripheral edges and intermediate spaces of the pixel regions).
With respect to Claim 6, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 5, wherein orthographic projections of the transistors at least partially overlap with orthographic projections of the edge signal transmission lines on the substrate (Yang: Para. [0213], orthographic projections of the signal lines and semiconductor layers overlapping to form active components).
With respect to Claim 7 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 6, wherein a gate of the transistor multiplexes a portion of a line segment of a corresponding edge signal transmission line (Yang: Para. [0274], the gate electrode line overlapping the channel region to integrally form the thin film transistor).
With respect to Claim 8, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 1, wherein at least in an overlapping area of the first connection line portion and the first transmission line portion, a line width of the first connection line portion is smaller than a line width of the second connection line portion (Yang: Para. [0005], claim 1, the width of the power line located in the first overlapping region is less than the width of the power line located in the second non-overlapping region).
With respect to Claim 9, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 8, wherein the device connection line includes a body extending portion and a narrowing portion, and a width of the narrowing portion is less than a width of the body extending portion (Yang: Para. [0007], [0015], the power line includes a body extending portion and a narrowing portion, wherein the narrowing portion overlaps the reset signal line).
With respect to Claim 10, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 9, wherein parallel connection line portions are connected in parallel with the second connection line portion and arranged to at least partially overlap in an extension direction (Yang: Para. [0112], fifth and sixth conductive portions connected separately and forming a reticular/parallel structure to reduce line resistance).
With respect to Claim 11 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 1, wherein the first connection line portion includes at least one hollow hole overlapping the first transmission line portion (Cheng: Para. [0008], claim 1, a gate cutout is disposed in an area of the gate line intersecting the data line).
Therefore, it would be obvious to one of ordinary skill in the art to modify the display panel, as taught by Kim and Yang, to incorporate a connection hollowed hole etched through the metal at the overlapping intersection, as taught by Cheng, in order to reduce the overlapped area and minimize the coupling capacitance between the transmission lines, thereby reducing crosstalk and signal delay in the high-density layout (Cheng: Para. [0030], [0064]).
With respect to Claim 12 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 11, wherein a width of the connection hollowed hole is greater than the width of the first transmission line portion, and orthographic projections of inner walls on both sides of the connection hollowed hole on the substrate are both located outside an orthographic projection of the first transmission line portion (Cheng: Para. [0048], a source cutout 13 is formed in an area where the source connecting line 12 intersects the gate cutout 3, and an orthographic projection of the source cutout 13 on the substrate is within an orthographic projection of the gate cutout 3, effectively eliminating direct parallel-plate overlap of the crossing traces to reduce parasitic capacitance).
With respect to Claim 13 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 3, wherein the first partial circuit includes a pulse width modulation unit, the second partial circuit includes an amplitude modulation unit, the pulse width modulation unit includes the first transistor, the amplitude modulation unit includes the driving transistor, and a second terminal of the first transistor is electrically connected to the gate of the driving transistor (Kim: Para. [0119], [0180], PWM driving circuit 710 with transistor T3 connected to the PAM driving circuit 720 with driving transistor T8); and wherein the gate device connection line is insulated and crossed with an i-th intermediate signal transmission line to a j-th intermediate signal transmission line (Yang: Para. [0005], claim 1, first gate electrode layer and first conductive layer intersecting and extending in first and second directions separated by insulating layers).
With respect to Claim 14, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 13, wherein the plurality of signal transmission lines include a first to fourth edge signal transmission line, a first to fifth intermediate signal transmission line, and a fifth edge signal transmission line arranged in sequence (Yang: Para. [0275]; Fig. 30A-D, arranging multiple signal transmission lines including reset, gate, data, and initialization lines in a parallel sequence spanning the edges and intermediate spaces of the pixel units to route signals sequentially).
With respect to Claim 15, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 14, wherein the pulse width modulation unit includes a sequence of transistors including a third, sixth, fourth, second, fifth, and first transistor, and the amplitude modulation unit includes a ninth, eighth, seventh, and twelfth transistor (Kim: Para. [0231], [0233], [0243], Fig. 16, a 13-transistor circuit with T1-T13 assigned to initialization, compensation, and light-emitting control functions matching the claimed hybrid configuration).
With respect to Claim 16 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 15, wherein specific orthographic overlapping of each individual numbered transistor occurs with its respective control signal line (Yang: Para. [0017], [0274], explicitly detailing how the semiconductor layer units overlap with the reset signal line and gate electrode line to form the respective active thin film transistors). It would be obvious to a PHOSITA to layout the 13T schematic of Kim using the integral overlapping formation taught by Yang.
With respect to Claim 17, the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 16, wherein the first reference voltage line includes a first and second sub-reference voltage line (Yang: Para. [0112], splitting conductive routing portions into multiple parallel sub-lines extending along the first and second directions to form a reticular structure that reduces line resistance).
With respect to Claim 18 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches the display panel of claim 3, wherein the first partial circuit includes a pulse width modulation unit, the second partial circuit includes an amplitude modulation unit (Kim: Para. [0119], [0180], PWM driving circuit 710 with transistor T3 connected to the PAM driving circuit 720 with driving transistor T8), and the gate device connection line is insulated and crossed with the first to N-th intermediate signal transmission lines (Yang: Para. [0005], claim 1, first gate electrode layer and first conductive layer intersecting and extending in first and second directions separated by insulating layers). The rationale for this rejection is identical to the rationale applied above to Claim 13.
With respect to Claim 23 (Currently Amended), the combination of Kim as modified by Yang and Cheng teaches an electronic device, comprising the display panel of claim 1 (Kim: Para. [0073], display panel applied to a wearable device, a portable device, a handheld device, and an electronic product).
Response to Arguments/Amendments/Remarks
Applicant’s arguments with respect to claims 1-23 have been considered but are moot because the arguments do not apply to the combination of references used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/BRYAN EARLES/Primary Examiner, Art Unit 2625
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