CTNF 19/213,123 CTNF 99320 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority This application is the Continuation in Part of U.S. Application Number 18/038,197 filed on 05/22/2023 which is the U.S. national stage of PCT/CN2020/131918 filed on November 26, 2020. Drawings The 5-page drawings have been considered and placed on record in the file. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time-wise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). In order to expedite the processing/approval of the terminal disclaimer, Applicants may choose to file an electronic terminal disclaimer (eTerminal Disclaimer) by referring to the following website: http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp The Claims 1, 15, and 20 of the instant application are rejected on the grounds of nonstatutory double patenting as being unpatentable over claims of its parent U.S. Patent Application No. 18/038,197. Although the conflicting claims 1, 15, and 20 are not identical to their corresponding parent U.S. patent application claims, they are not patentably distinct from each other, because claims of the instant application are broader in scope than the claims of the parent application, i.e., claims of the instant application are generic to all that is recited in claims of the above-listed parent U.S. patent application. Therefore, the present rejection of claims is based on anticipatory-type of non-statutory double patenting. For example, the following chart compares Claim 1 of the instant application with Claim 1 of the Patent Application No. 18/038,197. Instant Application Parent Application No. 18/038,197 Claim 1. A method for identifying a defect grade of a bad picture, comprising: obtaining the bad picture comprising a defect, of a detected product; determining a defect type of the defect in the bad picture by a neural network model; determining a defect size of the defect from the bad picture; determining a size of a pattern corresponding to a component that is adjacent to a position of the defect; and determining the defect grade of the defect according to the defect type of the defect and a magnitude relationship between the defect size and the size, wherein the defect grade is a degree to which the defect affects product yield. Claim 1. A method for identifying a defect grade of a bad picture, comprising: determining a defect size of a defect from the bad picture; according to a product model corresponding to the bad picture, determining a design size of a pattern corresponding to a component that is adjacent to a position of the defect; and determining the defect grade of the defect according to a defect type of the defect and a magnitude relationship between the defect size and the design size, wherein the defect grade is a degree to which the defect affects product yield; wherein the determining the defect grade of the defect according to the defect type of the defect and the magnitude relationship between the defect size and the design size, comprises: determining the defect type of the defect by a neural network model in an automatic defect classification system, and determining a determination condition of the defect grade used for the defect; wherein in a case that the bad picture is a bad picture in a display panel, the defect type comprises a particle defect and a passivation open defect; obtaining a determination result by comparing a ratio of the defect size to the design size with a set magnification according to the determination condition; and determining the defect grade according to the determination result; wherein the determining the defect type of the defect by the neural network model in the automatic defect classification system, and determining the determination condition of the defect grade used for the defect, comprises: in a case that the defect type is the particle defect, determining to use a determination condition of the particle defect for the bad picture, wherein a value of the set magnification ranges from 1.3 to 1.7; in a case that the defect type is the passivation open defect, determining to use a determination condition of the passivation open defect for the bad picture, wherein a value of the set magnification ranges from 0.8 to 1.2. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as follows. Claim 20 recites a readable storage medium comprising a memory. The broadest reasonable interpretation of a computer-readable storage medium also comprises transitory forms of signal transmission, signals per se, such as a propagating electrical or electromagnetic signal or carrier wave which is not one of the statutory categories of invention. MPEP § 2106. The Examiner suggests that Claim 20 should be rephrased as: "A non-transitory computer-readable storage medium…" in order to overcome this rejection. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more, and the claimed invention is directed to non-statutory subject matter as follows. The independent claims recite obtaining a picture of a defect of a product, determining a defect type by a neural network model, determining a defect size from the picture, determining a size of a pattern adjacent to the defect, determining a defect grade according to the type and relationship between the defect size and the pattern size, and the defect grade affects the product yield. Step 1: With regard to Step 1, the instant claims are directed to a method, which is among the statutory categories of invention. Step 2A – Prong 1: With regard to Step 2A – Prong 1, for example in Claim 1, the limitations of "determining a defect size of the defect from the bad picture; determining a size of a pattern corresponding to a component that is adjacent to a position of the defect; and determining the defect grade of the defect according to the defect type of the defect and a magnitude relationship between the defect size and the size, wherein the defect grade is a degree to which the defect affects product yield”, as drafted only involves mental processes, such as determining a defect size and design size of a pattern, or mathematical calculations, such as determining the defect grade based on a magnitude relationship. That is, nothing in the above-described claim elements preclude the steps from practically being performed in the mind or on a piece of paper. If a claim limitation, under its broadest reasonably interpretation covers performance of the limitation in the mind or through mathematical calculations, but for the recitation of a generic apparatus components, such as a processor, then it falls within the "mental processes", which include concepts performed in the human mind, including an observation, evaluation, judgement, opinion, or mathematical calculations groupings of the abstract idea. Accordingly, the claim recites an abstract idea. Step 2A – Prong 2: The 2019 PEG defines the phrase “integration into a practical application” to require an additional element or a combination of additional elements in the claim to apply, rely on, or use the judicial exception. In the instant case, the additional elements in the claims do not apply, rely on, or use the judicial exception. This judicial exception is not integrated into a practical application because the claim only recites the following additional step "A method for identifying a defect grade of a bad picture, comprising: obtaining the bad picture comprising a defect, of a detected product; determining a defect type of the defect in the bad picture by a neural network model”, i.e., insignificant extra-solution activity. The other additional recited element in certain other claims is just a processor and a computer-readable storage medium, which are generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because it is a field-of-use limitation that does not impose any meaningful limits on practicing the abstract idea. Therefore, the claim as a whole, recites an abstract idea. Step 2B: Because the claim fails under Step 2A, the claims are further evaluated under Step 2B. The claim herein does not include additional steps that are sufficient to amount to significantly more than the judicial exception because as discussed above with respect to integration of the abstract idea into practical application, the additional elements/steps amount to no more than insignificant extra-solution activities. Mere instructions to apply an exception using generic apparatus component, such as a processor, cannot provide an inventive concept. The claim is not patent eligible. It should be noted that a similar analysis may be performed with respect to independent Claims 15 and 20. Further, with regard to dependent Claims 2-14 and 16-19 viewed individually, these additional steps are under their broadest reasonable interpretation, cover performance of the limitation in the mind and do not provide meaningful limitations to transform the abstract idea into a patent eligible application of the abstract idea such that the claims limitations amount to significantly more than the abstract idea itself. For example, determining a maximum length of a defect in perpendicular directions as the defect size as recited in Claim 7 or labeling defects of different grades with different labels as recited in Claim 14 are only examples of routine and conventional image processing steps or steps that could be completed within the human mind and do not amount to significantly more to consider as inventive steps. Accordingly, Claims 1-20 are rejected under 35 U.S.C. 101. Examiner recommends to amend independent claims to recite the training of the neural network as well as how the system automatically classifies defects as recited in the specification to attempt to overcome this rejection. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-9 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leu et al. (US 20200026819 A1) in view of Bennett et al. (US 20200384693 A1) . Regarding Claim 1, Leu teaches "A method for identifying a defect grade of a bad picture, comprising: obtaining the bad picture comprising a defect, of a detected product"; (Leu, Para. 90, teaches a defect inspection tool which runs a defect scan and inspection on the wafer and generate an inspection data file including defect size dimension, shape, area, die index, coordinate, and image, i.e., obtain a bad picture comprising a defect of a detected product being the scan image of the wafer containing a defect); " determining a defect type of the defect in the bad picture by a neural network model "; "determining a defect size of the defect from the bad picture"; (Leu, Para. 90, teaches a defect inspection tool which runs a defect scan and inspection on the wafer and generate an inspection data file including defect size dimension, shape, area, die index, coordinate, and image, i.e., determine defect size of the defect from the defect scan image file); "determining a size of a pattern corresponding to a component that is adjacent to a position of the defect"; (Leu, Fig. 6B [1101-1102] and Paras. 98-100, teaches determining dimension size of the layout patterns wherein the defect is adjacent to the given layout pattern, i.e., determine a design size of the pattern corresponding to the component adjacent to the defect according to the product model); " and determining the defect grade of the defect according to the defect type of the defect and a magnitude relationship between the defect size and the size "; "wherein the defect grade is a degree to which the defect affects product yield"; (Leu, Para. 12, teaches determining a wafer yield level by combining all the defect processes together, i.e., defect grade is a degree that the defect affects the product yield). However, Leu does not explicitly teach "determining a defect type of the defect in the bad picture by a neural network model; and determining the defect grade of the defect according to the defect type of the defect and a magnitude relationship between the defect size and the size”. In an analogous field of endeavor, Bennett teaches "determining a defect type of the defect in the bad picture by a neural network model"; (Bennett, Abstract and Paras. 22 and 29, teaches using a machine learning system using a neural network to form a classification model to learn how to map image regions to a particular class or type of defect wherein training data has additional severity levels in which the machine learning algorithm is able to make quantitative and comparative assessments and make robust determinations on the severity of indications, i.e., determine defect type of the defect in the bad picture through the use of a neural network); "and determining the defect grade of the defect according to the defect type of the defect and a magnitude relationship between the defect size and the size"; (Bennett, Para. 32, teaches determining a severity of any identified defects based on the amount of deviation from nominal, the size of a defect, and the total size of a defect compared to the area evaluated wherein the defect type and size are evaluated to be relevant to impact the quality of the workpiece, i.e., determine defect grade according to defect type and a magnitude relationship between the defect size and the pattern size). Regarding Claim 2, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the detected product comprises at least one of a display panel, a circuit board, or a chip"; (Leu, Paras. 3, 85, and 90, teaches defects will occur in the manufacturing procedures of the wafer which is why the Fab will use a defect inspection tool wherein there comprises a flat panel displayFab and a printed circuit board Fab and wherein the wafer is a wafer chip, i.e., detect product comprises a display panel, a circuit board, or a chip). Regarding Claim 3, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the component that is adjacent to the position of the defect comprises at least one of a device, a wiring, or a film layer around the defect"; (Leu, Fig. 6B [1101-1102] and Paras. 92 and 98-100, teaches determining dimension size of the layout patterns wherein the defect is adjacent to the given layout pattern wherein the design layout pattern includes a device layout pattern which always includes a layout pattern layer, i.e., component adjacent to the defect comprises at least a device or layer around the defect). Regarding Claim 4, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the determining the size of the pattern corresponding to the component that is adjacent to the position of the defect, comprises: determining the size of the pattern corresponding to the component that is adjacent to the position of the defect according to a product model corresponding to the bad picture"; (Leu, Fig. 6B [1101-1102] and Paras. 98-100, teaches determining dimension size of the layout patterns wherein the defect is adjacent to the given layout pattern, i.e., determine a design size of the pattern corresponding to the component adjacent to the defect according to the product model). Regarding Claim 5, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the determining the size of the pattern corresponding to the component that is adjacent to the position of the defect, comprises: determining the size of the pattern corresponding to the component that is adjacent to the position of the defect according to the position of the defect detected from the bad picture"; (Leu, Fig. 3C and 6B [1101-1102] and Paras. 98-100, teaches the dimension size of the defect layout pattern is determined by the defect inspection tool's precision level or deviation range in which the defect image of the defects is converted to the defect layout pattern with corresponding defect coordinates, i.e., size of pattern that is adjacent to the position of the defects is determined according to the position of the defect). Regarding Claim 6, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the defect grade comprises at least one of bad with quality risk, bad without quality risk, bad and repairable, or bad and unrepairable"; (Bennett, Paras. 28 and 32, teaches designating severity level classifications to defects such as low, medium, and high wherein the defect type and size may be determined to be relevant enough to impact the quality of the workpiece in which the additive manufacturing system can take necessary actions such as correcting the powder layer via recoating or aborting the build process outright, i.e., defect grade being severity comprises at least bad with or without quality risk as well as bad and repairable or unrepairable with correct powder recoating or aborting the build). The proposed combination as well as the motivation for combining the Leu and Bennett references presented in the rejection of Claim 1, applies to claim 6. Thus, the method recited in claim 6 is met by Leu in view of Bennett. Regarding Claim 7, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the determining the defect size of the defect from the bad picture, comprises: determining a maximum length of the defect in a first direction and a second direction as the defect size, wherein the first direction is perpendicular to the second direction"; (Leu, Para. 98, teaches recording each defect image's content including rough defect image dimension including the maximum size in X direction and Y direction, i.e., determine maximum length of the defect size and a first and second direction that are perpendicular). Regarding Claim 8, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein the determining the defect grade of the defect according to the defect type of the defect and the magnitude relationship between the defect size and the size, comprises: determining a determination condition of the defect grade used for the defect according to the defect type of the defect"; (Bennett, Abstract and Paras. 28 and 32, teaches comparing an image of the powder bed to a set of training data in which deviations from the nominal model are determined and any deviations greater than a threshold are labelled and identified as a defect which includes its type and severity wherein severity levels include low, medium and high and each patch is labeled by the type of defect and wherein a severity of any identified defects can be determined and assigned to the particular defect in which the defect type and size may be relevant enough to impact the quality of the workpiece and prompt necessary action, i.e., determine condition of the defect grade being the severity according to the defect type being the particular defect with an evaluated deviation being enough to prompt a type of action); "and calculating a ratio of the defect size to the size of the pattern corresponding to a component that is adjacent to the position of the defect"; (Leu, FIG. 7D and Para. 109, teaches the system judging short circuit failure or open circuit failure probability as the Killer Defect Index of a defect wherein the system overlaps every clipped polygon defect image to the mapped defect layout pattern wherein the dimensions of the defect image is compared to the dimensions of the pattern, i.e., calculate a ratio being the KDI of the defect size to the pattern size adjacent to the defect); "and determining the defect grade of the defect by comparing the ratio with a set magnification"; (Bennett, Para. 32, teaches determining a severity of a defect in which deviations are compared and evaluated as greater than a numerical threshold in which the defect type and size may be relevant enough to impact quality and prompt necessary action, i.e., determining defect grade being the severity by comparing the ratio being the compared total size of the defect to the area with a set numerical threshold). The proposed combination as well as the motivation for combining the Leu and Bennett references presented in the rejection of Claim 1, applies to claim 8. Thus, the method recited in claim 8 is met by Leu in view of Bennett. Regarding Claim 9, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein in a case that the bad picture is a bad picture in a display panel, the defect type comprises at least one of a particle defect or a passivation open defect"; (Leu, Paras. 3 and 139, teaches LED Fab wherein random and systematic defects are produces because of resolution deviation of equipment, abnormal incidence, particle induced in a process, pattern defect in the design layout pattern, and insufficient lithograph process window wherein defects are present in the passivation layer as well that cause open failure die, i.e., picture in a display panel in which the defect type comprises a particle defect or a passivation open defect). Regarding Claim 14, the combination of references of Leu in view of Bennett teaches "The method according to claim 1, wherein after determining the defect grade of the defect, the method further comprises: labeling defects of different defect grades with different labels"; (Bennett, Abstract, teaches labeling defects including its type and severity, i.e., labeling defects of different defect grades with different labels). The proposed combination as well as the motivation for combining the Leu and Bennett references presented in the rejection of Claim 1, applies to claim 14 Thus, the method recited in claim 14 is met by Leu in view of Bennett. Claim 15 recites an apparatus with elements corresponding to the steps recited in Claim 1. Therefore, the recited elements of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding method claim. Additionally, the rationale and motivation to combine the Leu and Bennett references, presented in rejection of Claim 1, apply to this claim. Finally, the combination of the Leu and Bennett references discloses a processor and a memory to execute instructions (for example, see Bennett, Paragraph 27). Claim 16 recites an apparatus with elements corresponding to the steps recited in Claim 2. Therefore, the recited elements of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding method claim. Additionally, the rationale and motivation to combine the Leu and Bennett references, presented in rejection of Claim 1, apply to this claim. Finally, the combination of the Leu and Bennett references discloses a processor and a memory to execute instructions (for example, see Bennett, Paragraph 27). Claim 17 recites an apparatus with elements corresponding to the steps recited in Claim 3. Therefore, the recited elements of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding method claim. Additionally, the rationale and motivation to combine the Leu and Bennett references, presented in rejection of Claim 1, apply to this claim. Finally, the combination of the Leu and Bennett references discloses a processor and a memory to execute instructions (for example, see Bennett, Paragraph 27). Claim 18 recites an apparatus with elements corresponding to the steps recited in Claim 4. Therefore, the recited elements of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding method claim. Additionally, the rationale and motivation to combine the Leu and Bennett references, presented in rejection of Claim 1, apply to this claim. Finally, the combination of the Leu and Bennett references discloses a processor and a memory to execute instructions (for example, see Bennett, Paragraph 27). Claim 19 recites an apparatus with elements corresponding to the steps recited in Claim 5. Therefore, the recited elements of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding method claim. Additionally, the rationale and motivation to combine the Leu and Bennett references, presented in rejection of Claim 1, apply to this claim. Finally, the combination of the Leu and Bennett references discloses a processor and a memory to execute instructions (for example, see Bennett, Paragraph 27). Claim 20 recites a computer-readable storage medium storing a program with instructions corresponding to the steps recited in Claim 1. Therefore, the recited programming instructions of this claim are mapped to the proposed combination in the same manner as the corresponding steps in its corresponding method claim. Additionally, the rationale and motivation to combine the Leu and Bennett references, presented in rejection of Claim 1, apply to this claim. Finally, the combination of the Leu and Bennett references discloses a computer readable storage medium (for example, see Bennett, Paragraph 27) . 07-21-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Leu in view of Bennett and Xu et al. (US 20120027286 A1) . Regarding Claim 10, the combination of references of Leu in view of Bennett teaches "The method according to claim 9, further comprising: determining the defect grade of the defect according to a pattern around the position of the defect"; (Leu, FIG. 7D and Para. 109, teaches the system judging short circuit failure or open circuit failure probability as the Killer Defect Index of a defect wherein the system overlaps every clipped polygon defect image to the mapped defect layout pattern wherein the dimensions of the defect image is compared to the dimensions of the pattern, i.e., determine the defect grade being the KDI probability of causing failure according to the pattern around the defect). However, the combination of references of Leu in view of Bennett does not explicitly teach "wherein the pattern around the position of the defect comprises at least one of a pattern corresponding to a channel of a thin film transistor, a pattern corresponding to an intersection of gate lines and data lines of the display panel, or a pattern corresponding to data lines in the display panel". In an analogous field of endeavor, Xu teaches "wherein the pattern around the position of the defect comprises at least one of a pattern corresponding to a channel of a thin film transistor, a pattern corresponding to an intersection of gate lines and data lines of the display panel, or a pattern corresponding to data lines in the display panel"; (Xu, Paras. 25 and 29, teaches defect classification with respect to landmarks within the flat panel display such as gate lines, drain lines, and source lines and wherein a TFT-defect connectivity measure indicates the connectivity between the defect and a TFT, i.e., pattern around defect position comprises thin film transistor channels or data lines in a display panel). It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the invention of Leu and Bennett by including the pattern around the defect comprising thin film transistor channel and gate and data lines of the display panel taught by Xu. One of ordinary skill in the art would be motivated to combine the references since it ensures quality and improves yield (Xu, Para. 2, teaches the motivation of combination to be to ensure display quality and improve yield). Thus, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Leu in view of Bennett and Noda (WO 2010070755 A1) . Regarding Claim 11, the combination of references of Leu in view of Bennett does not explicitly teach "The method according to claim 10, wherein the determining the defect grade of the defect according to the pattern around the position of the defect, comprises: in a case that the pattern around the position of the defect is the pattern corresponding to the channel of the thin film transistor, if a ratio of the defect size to a size of the channel is less than or equal to a set magnification, determining that the defect grade is bad with quality risk; if the ratio of the defect size to the size of the channel is greater than the set magnification, determining that the defect grade is bad without quality risk". In an analogous field of endeavor, Noda teaches "The method according to claim 10, wherein the determining the defect grade of the defect according to the pattern around the position of the defect, comprises: in a case that the pattern around the position of the defect is the pattern corresponding to the channel of the thin film transistor, if a ratio of the defect size to a size of the channel is less than or equal to a set magnification, determining that the defect grade is bad with quality risk; if the ratio of the defect size to the size of the channel is greater than the set magnification, determining that the defect grade is bad without quality risk"; (Noda, Abstract and Pg. 8 Paras. 9-11, teaches calculating the defectiveness of each dot for each TFT channel wherein the size of the defect candidate region is compared with the size of the TFT array as a third threshold and if the size of the defect is smaller than the third threshold it is determined as not a true defect, i.e., pattern around defect is a channel of the thin film transistor and a ratio of defect size to the size of the channel being the compared defect size to the TFT array size compared to threshold is used to determine if the defect grade or defectiveness is with or without quality risk being the determination of a true defect or just noise). It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the invention of Leu and Bennett by including the pattern around the defect comprising thin film transistor channels and the defect grade is determined by comparing the size of the defect and size of the channel to a threshold taught by Noda. One of ordinary skill in the art would be motivated to combine the references since it reduces error detection (Noda, Abstract, teaches the motivation of combination to be to reduce error detection of defects). Thus, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW STEVEN BUDISALICH whose telephone number is (703)756-5568. The examiner can normally be reached Monday - Friday 8:30am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amandeep Saini can be reached on (571) 272-3382. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. ANDREW S BUDISALICH/Examiner, Art Unit 2662 /AMANDEEP SAINI/Supervisory Patent Examiner, Art Unit 2662 Application/Control Number: 19/213,123 Page 2 Art Unit: 2662 Application/Control Number: 19/213,123 Page 3 Art Unit: 2662 Application/Control Number: 19/213,123 Page 4 Art Unit: 2662 Application/Control Number: 19/213,123 Page 5 Art Unit: 2662 Application/Control Number: 19/213,123 Page 6 Art Unit: 2662 Application/Control Number: 19/213,123 Page 7 Art Unit: 2662 Application/Control Number: 19/213,123 Page 8 Art Unit: 2662 Application/Control Number: 19/213,123 Page 9 Art Unit: 2662 Application/Control Number: 19/213,123 Page 10 Art Unit: 2662 Application/Control Number: 19/213,123 Page 11 Art Unit: 2662 Application/Control Number: 19/213,123 Page 12 Art Unit: 2662 Application/Control Number: 19/213,123 Page 13 Art Unit: 2662 Application/Control Number: 19/213,123 Page 14 Art Unit: 2662 Application/Control Number: 19/213,123 Page 15 Art Unit: 2662 Application/Control Number: 19/213,123 Page 16 Art Unit: 2662 Application/Control Number: 19/213,123 Page 17 Art Unit: 2662 Application/Control Number: 19/213,123 Page 18 Art Unit: 2662 Application/Control Number: 19/213,123 Page 19 Art Unit: 2662 Application/Control Number: 19/213,123 Page 20 Art Unit: 2662 Application/Control Number: 19/213,123 Page 21 Art Unit: 2662 Application/Control Number: 19/213,123 Page 22 Art Unit: 2662 Application/Control Number: 19/213,123 Page 23 Art Unit: 2662
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