DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the first compensation circuit comprises one or more capacitors, each capacitor of the one or more capacitors comprises a first terminal that is configured to be coupled with the clock signal path via a transistor and a second terminal coupled with a ground voltage source via a respective variable resistance component” as recited in claims 2 and 19; and “wherein the second compensation circuit comprises one or more capacitors, each capacitor of the one or more capacitors comprises a first terminal that is configured to be coupled with the clock signal path via a transistor and a second terminal coupled with a supply voltage source via a respective variable resistance component” as recited in claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: In paragraph [0042], line 1, “415” should be changed to “420” to match the description for the elements in the Figure (see Figure 4, compensation component 420).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 2, the recitation “wherein the first compensation circuit comprises one or more capacitors, each capacitor of the one or more capacitors comprises a first terminal that is configured to be coupled with the clock signal path via a transistor and a second terminal coupled with a ground voltage source via a respective variable resistance component” is indefinite because it is inconsistent with what is disclosed and shown in the drawings. Figure 4 of drawings discloses a first compensation circuit (415) including one or more capacitors (440-A, 440-B), each capacitor of the one or more capacitors (440-A, 440-B) comprises a first terminal that is configured to be coupled with the clock signal path (capacitors 440-A and 440-B directly coupled to the clock signal path (230-A, 230-B), i.e., not via a transistor as recited in the claim) and a second terminal coupled with a ground voltage source via a respective variable resistance component (445-A, 445-B). Thus, the recitation “each capacitor of the one or more capacitors comprises a first terminal that is configured to be coupled with the clock signal path via a transistor” in the above phrase is indefinite, and it is suggested to delete “via a transistor” on line 3 of the claim. Clarification and/or appropriate correction is required.
Claims 3-5 are indefinite because they depend on claim 2.
For claim 18, the recitation “a current mirror” on line 7 is indefinite because it is not unclear antecedent basis since it is not clear if it is the same as “a current mirror” recited earlier on line 4. Clarification and/or appropriate correction is required.
Claims 19-20 are indefinite because they depend on claim 18.
Also, for claims 19-20, these claims are indefinite for the similar reasons as discussed in claim 2 above, i.e., Figure 4 of the drawings discloses a first compensation circuit (415) including one or more capacitors (440-A, 440-B), wherein each capacitor of the one or more capacitors (440-A, 440-B) comprises a first terminal that is configured to be coupled with the clock signal path (capacitors 440-A and 440-B directly coupled to the clock signal path (230-A, 230-B), i.e., not via a transistor as recited in the claim) and a second terminal coupled with a ground voltage source via a respective variable resistance component (445-A, 445-B). Figure 4 of the drawings also discloses a second compensation circuit (420) including one or more capacitors (455-A, 455-B), wherein each capacitor of the one or more capacitors (455-A, 455-B) comprises a first terminal that is configured to be coupled with the clock signal path (capacitors 455-A and 455-B directly coupled to the clock signal path (230-A, 230-B), i.e., not via a transistor as recited in the claim) and a second terminal coupled with a supply voltage source via a respective variable resistance component (460-A, 460-B). Thus, the recitation “via a transistor” on line 3 in claim 19 and in claim 20 is indefinite, and it is suggested to delete “via a transistor” on line 3 of claim 19 and of claim 20. Clarification and/or appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 13 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwamoto et al. (USP 5,731,727).
For claim 1, Figures 1, 2, 5 and 12 teaches an apparatus (Voltage Delay circuit 35 in Figure 5, wherein the detail is shown in each of Figures 1, 2 and 12), comprising: a clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12) configured to communicate a clock signal (ECLK), the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12) comprising an input (ECLK), an output (ECLK’), and one or more components (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12) associated with delaying the clock signal (ECLK) between the input and the output; and a delay adjustment circuit (71-73, 81.1, 81.2 … 81.K, 84.1, 84.2 … 84.K) configured to modify the clock signal (ECLK) at the output (ECLK’) of the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12) with the clock signal (ECLK) at the input of the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12), the delay adjustment circuit (71-73, 81.1, 81.2 … 81.K, 84.1, 84.2 … 84.K) comprising: a first compensation circuit (84.1, 84.2 … 84.K) coupled with the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12), the first compensation circuit (84.1, 84.2 … 84.K) configured to modify a delay of the clock signal (ECLK) based at least in part on a first control signal (signal at gate of 84.1, 84.2 … 84.K); a second compensation circuit (81.1, 81.2 … 81.K) coupled with the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12), the second compensation circuit (81.1, 81.2 … 81.K) configured to modify the delay of the clock signal (ECLK) based at least in part on a second control signal (signal at gate of 81.1, 81.2 … 81.K); and a current mirror (71-73) coupled with a supply voltage source (Vcc), the first compensation circuit (84.1, 84.2 … 84.K), and the second compensation circuit (81.1, 81.2 … 81.K), the current mirror (71-73) configured to output the first control signal (signal at gate of 84.1, 84.2 … 84.K) to the first compensation circuit (84.1, 84.2 … 84.K) and output the second control signal (signal at gate of 81.1, 81.2 … 81.K) to the second compensation circuit (81.1, 81.2 … 81.K).
For claim 10, Figures 1, 2, 5 and 12 teaches an apparatus (Voltage Delay circuit 35 in Figure 5, wherein the detail is shown in each of Figures 1, 2 and 12), further comprising: a control signal component (73 in Figure 1, 2 and 12, and the Loop Filter 34 that generates signal VCOin in Figure 5; and 101 (for Figure 1) and (111 for Figure 2)) coupled with the first compensation circuit (84.1, 84.2 … 84.K), the second compensation circuit (81.1, 81.2 … 81.K), and the current mirror (71-73), the control signal component (73 in Figure 1, 2 and 12, and the Loop Filter 34 that generates signal VCOin to the gate of 73 in Figure 5; and 101 (for Figure 1) and (111 for Figure 2)) configured to modify the first control signal (signal at gate of 84.1, 84.2 … 84.K) and the second control signal (signal at gate of 81.1, 81.2 … 81.K) to reduce variations in the delay based at least in part on variations a voltage of the supply voltage source (Vcc).
For claim 13, Figures 1, 2, 5 and 12 teaches an apparatus (Voltage Delay circuit 35 in Figure 5, wherein the detail is shown in each of Figures 1, 2 and 12), wherein each component (component 82.1-83.1; component 82.2-83.2; … and component 82.K-83.K in Figures 1, 2 and 12) associated with delaying the clock signal (ECLK) comprises a respective inverter (inverter 82.1-83.1; inverter 82.2-83.2; … and inverter 82.K-83.K in Figures 1, 2 and 12).
For claim 18, Figures 1, 2, 5 and 12 teaches an apparatus (Voltage Delay circuit 35 in Figure 5, wherein the detail is shown in each of Figures 1, 2 and 12), comprising:
receiving, at a clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12), a clock signal (ECLK);
modifying the clock signal (ECLK) using a first compensation circuit (84.1, 84.2 … 84.K) coupled with the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12) and a current mirror (71-73) based at least in part on receiving, at the first compensation circuit (84.1, 84.2 … 84.K), a first control signal (signal at gate of 84.1, 84.2 … 84.K) from the current mirror (71-73);
modifying the clock signal (ECLK) using a second compensation circuit (81.1, 81.2 … 81.K) coupled with the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12) and a current mirror (71-73) based at least in part on receiving, at the second compensation circuit (81.1, 81.2 … 81.K), a second control signal (signal at gate of 81.1, 81.2 … 81.K) from the current mirror (71-73); and
transmitting, from the clock signal path (82.1-83.1, 82.2-83.2 … 82.K-83.K in Figures 1, 2 and 12), the clock signal modified by the first compensation circuit (84.1, 84.2 … 84.K) and the second compensation circuit (81.1, 81.2 … 81.K).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto et al. (USP 5,731,727) in view of Lee et al. (US 2008/0101521) and further in view of Matsuura et al. (US 2005/0083105).
For claim 11, Figures 1, 2, 5 and 12 of Iwamoto et al. teaches an apparatus (Voltage Delay circuit 35 in Figure 5, wherein the detail is shown in each of Figures 1, 2 and 12), comprising all the limitations of this claim (as discussed above in the rejection of claim 10) except for wherein the control signal component (73 in Figure 1, 2 and 12, and the Loop Filter 34 that generates signal VCOin in Figure 5; and 101 (for Figure 1) and (111 for Figure 2)) comprises a variable resistor coupled in parallel with a variable capacitor. However, Figure 9 of Lee et al. teaches a loop filter comprising a variable resistor (VR1) coupled in parallel with a capacitor (C4) for the purpose of dynamically controlling/adjusting the loop bandwidth with change in frequency of the input signal (see [0057]-[0058]). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the apparatus in Figures 1, 2, 5 and 12 of Iwamoto et al. to use the specific loop filter (27) that comprises a variable resistor (VR1) coupled in parallel with a capacitor (C4), as taught in Figure 9 of Lee et al., to generate the signal VCOin to the gate of transistor 73 in Figures 1, 2 and 12 of Iwamoto et al. for the purpose of dynamically controlling/adjusting the loop bandwidth with change in frequency of the input signal (see [0057]-[0058]).
The combination/modification of Iwamoto et al. and Lee et al. as discussed above does not teach capacitor (C4) is a variable capacitor. However, Figure 1 of Matsuura et al. teaches a variable capacitor (VC), and it is obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the above combination/modification of Iwamoto et al. and Lee et al. so to use a variable capacitor (VC) as taught in Figure 1 of Matsuura et al. for the broad capacitor (C4) for the purpose of easily control the bandwidth of the loop filter to a desire value. Thus, this combination/modification (Iwamoto et al. in view of Lee et al. and Matsuura et al.) teaches all the limitation of claim 11.
For claim 12, the combination/modification (Iwamoto et al. in view of Lee et al. and Matsuura et al. as discussed in claim 11 above) teaches the variable resistor (VR1) comprises a plurality of transistors (S140, S141 … S14N-1, and it is obvious that transistor can be used to implement a switch in an integrated circuit, for example see transistor M1, M2, M3 … Mn in Figure 1 of Matsuura et al.) each transistor of the plurality of transistors (S140, S141 … S14N-1) configured to be activated based at least in part on a third control signal (signal Q(0), Q(1) … Q(N-1)); and the variable capacitor (VC in Figure 1 of Matsuura et al. that is used for C4 in Lee et al.) comprises a plurality of capacitors (VC1, VC2, VC3 … VCn), each capacitor of the plurality of capacitors (VC1, VC2, VC3 … VCn) configured to be activated based at least in part on a fourth control signal (Vcont).
Allowable Subject Matter
Claims 14-17 are allowed. The following is an examiner’s statement of reasons for allowance:
Claim 14 is allowed because the closet prior art (Iwamoto et al., USP 5,731,727) in Figures 1, 2, 5 and 12 (as discussed in the rejection of claim 1 above) fails to disclose or suggest the limitations “one or more first capacitors, each first capacitor of the one or more first capacitors coupled between the clock signal path and a respective first transistor of one or more first transistors; one or more second capacitors, each second capacitor of the one or more second capacitors coupled between the clock signal path and a respective second transistor of one or more second transistors; and a current mirror configured to output a first control signal to the one or more first transistors and output a second control signal to the one or more second transistor” in combination with other limitations as recited in claim 14.
Claims 15-17 are allowed because they depend on claim 14.
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 would be allowed because the closet prior art (Iwamoto et al., USP 5,731,727) in Figures 1, 2, 5 and 12 (as discussed in the rejection of claim 1 above) fails to disclose or suggest the limitations “wherein the second compensation circuit comprises one or more capacitors, each capacitor of the one or more capacitors comprises a first terminal coupled with the clock signal path and a second terminal coupled with the supply voltage source via a respective variable resistance component” as recited in claim 6.
Claims 7-9 would be allowed because they depend on claim 6.
Claims 2-5 and 19-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 2 and 19 would be allowed because the closet prior art (Iwamoto et al., USP 5,731,727) in Figures 1, 2, 5 and 12 (as discussed in the rejection of claims 1 and 18 above) fails to disclose or suggest the limitations “wherein the first compensation circuit comprises one or more capacitors, each capacitor of the one or more capacitors comprises a first terminal that is configured to be coupled with the clock signal path and a second terminal coupled with a ground voltage source via a respective variable resistance component” as recited in claims 2 and 19.
Claims 3-5 would be allowed because they depend on claim 2.
Claim 20 would be allowed because the closet prior art (Iwamoto et al., USP 5,731,727) in Figures 1, 2, 5 and 12 (as discussed in the rejection of claim 18 above) fails to disclose or suggest the limitations “wherein the second compensation circuit comprises one or more capacitors, each capacitor of the one or more capacitors comprises a first terminal coupled with the clock signal path and a second terminal coupled with the supply voltage source via a respective variable resistance component” as recited in claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamazaki et al. (US 2008/0164923) discloses disclose a delay circuit with first and second compensation circuit and current mirror to control the compensation circuit of the delay circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights