Prosecution Insights
Last updated: October 25, 2026
Application No. 19/213,745

SYSTEM AND METHOD FOR DESIGNING A POWER MANAGEMENT CONTROLLER USING A NO-CODE APPROACH

Non-Final OA §103
Filed
May 20, 2025
Priority
Aug 13, 2024 — RE 10-2024-0108213
Examiner
ZAMAN, FAISAL M
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Itda Semiconductor Co. Ltd.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
634 granted / 943 resolved
+12.2% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
29 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
65.5%
+25.5% vs TC avg
§102
15.4%
-24.6% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 943 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (U.S. Patent 7,954,078) and Lee et al. (U.S. Patent Application Publication Number 2015/0287444). Regarding Claims 1 and 11, Wang discloses a system for designing a power management controller using a no-code approach, the system comprising: a memory configured to store at least one instruction (Column 21, lines 53-57); a power manager component storage in which a root power manager component and at least one type of domain power manager component are stored (Column 7, lines 39-42); and at least one processor configured to execute the at least one instruction stored in the memory (Column 21, lines 53-57), wherein the at least one instruction includes instructions for: generating a root power manager instance (Figure 3, item 318, Column 7, lines 19-21) based on the root power manager component and generating at least one domain power manager instance (Figure 3, items 304, 306, 312, and 316) based on the at least one type of domain power manager component (Column 6, lines 64-67 and Column 7, lines 2-5; i.e., each instance 304, 306, 312, and 316 is associated with a particular power domain PD2-PD4), each constituting the power management controller (Figure 3, item 300, Column 6, lines 45-50); establishing a connection between an output port of the root power manager instance and an input port of the at least one domain power manager instance (Column 7, lines 19-21; i.e., the root power manager instance 318 communicates with each domain power manager instance 304, 306, 312, and 316, which would require the establishment of a connection using input and output ports); allocating a memory storage space for each of the root power manager instance and the at least one domain power manager instance (Column 7, lines 36-55; i.e., a computer readable storage is allocated for each of the various instances 304, 306, 312, 316, and 318); and generating hardware code of power elements included in the power management controller (Column 1, lines 41-51 and Column 5, line 63 - Column 6, line 5; i.e., hardware design language such as VHDL or Verilog), register code corresponding to each power element (Column 1, lines 41-51, Column 7, lines 36-55, and Table 3; i.e., register transfer level [RTL] code), hardware code corresponding to the ports and the connections (Column 9, lines 61-67; i.e., input/output [I/O] information is included in the hardware code), and code corresponding to an operation sequence of the power management controller (Column 9, lines 38-53). Wang does not expressly disclose that the code corresponding to an operation sequence of the power management controller is binary code. In the same field of endeavor (e.g., power manager code generation techniques), Lee teaches code corresponding to an operation sequence of the power management controller is binary code (paragraphs 0047-0048). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Lee’s teachings of power manager code generation techniques with the teachings of Wang, for the purpose of allowing the hardware to more quickly operate on the code because it would not need to translate the RTL code first. Regarding Claims 2 and 12, Wang discloses wherein the at least one instruction includes instructions for copying register field values and operation sequences of the root power manager component to the register field values and operation sequences of the root power manager instance, and copying register field values and operation sequences of at least one domain power manager component to the register field values and operation sequences of each corresponding domain power manager instance (Column 28, lines 1-4). Regarding Claims 3 and 13, Wang discloses wherein the at least one instruction includes instructions for setting, with respect to the root power manager instance, the number of domain groups and the number of power domains connected to each domain group (Column 7, lines 19-24). Regarding Claims 4 and 14, Wang discloses wherein the memory storage space allocated to the domain power manager instance is determined based on the number of domain groups and the number of power domains included in the domain group to which the domain power manager instance belongs (Column 7, lines 36-55). Regarding Claims 5 and 15, Wang discloses wherein the at least one instruction includes instructions for generating, for each of the at least one domain power manager instance, a power management interface instance connected to the domain power manager instance through a P-link (Figure 3, see connection between items 318 and 304/306/312/316; i.e., the link between the root power manager 318 and the domain power manager instances is equivalent to the claimed “P-link”). Allowable Subject Matter Claims 6-10 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claims 6 and 16, the prior art of record does not teach “generating at least one power instance that constitutes at least one power manager component selected from the root power manager component and the at least one type of domain power manager component, based on the at least one power component; generating a first instruction instance based on the at least one instruction component; determining a target power instance of the first instruction instance from among the at least one power instance, and setting a value for the first instruction instance; and generating code including an instruction, a register address, and data based on the first instruction instance, the target power instance, and the value” (as recited in Claim 6, and similarly in Claim 16) in conjunction with the other limitations in the claims. All claims that are not specifically addressed are allowable due to a dependency. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system for designing a power management controller using a no-code approach. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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Prosecution Timeline

May 20, 2025
Application Filed
Aug 19, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
80%
With Interview (+13.3%)
2y 10m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 943 resolved cases by this examiner. Grant probability derived from career allowance rate.

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