DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyamoto (US 20140169092).
Regarding claim 1, Miyamoto teaches A memory device comprising: a memory array comprising memory cells arranged into pages, rows, and columns, wherein each of the memory cells is respectively associated with a particular page, row, and column of the memory array (“a NAND flash memory 10 comprises a memory array 101, a page buffer 102, a column coding circuit 103, a main column repair multiplexer (a column repair circuit) 104, a parity column repair circuit (Parity CRMUX) 105, an ECC column coding circuit 108”); and a first column of the memory array is configured to store parity data for a first portion of the pages and to store column redundancy data for a second portion of the pages (“Also, the semiconductor memory device comprises a page buffer 102 (e.g., a fourth page buffer) that is replaced together with a parity memory cell and a bit line when the parity memory cell or the bit line connected to the third page buffer is defective, a column repair circuit 104 (e.g., a first repair circuit) that is connected to the second bus and repairs a page buffer, connected to a defective memory cell or bit line, from among the first page buffer with the second page buffer” ¶302).
Regarding claim 2, Miyamoto teaches further comprising: a column redundancy bus; (“By this, it is possible to control column coding, that is, addresses independently by preparing a plurality of data buses (e.g., the ECC bus and the data bus). In exemplary embodiments, it is possible to control addresses independently by forming a data bus to be independent from input/output lines of the page buffer” ¶164); an error correction circuit including a parity bit input (“the page buffer 102c is a page buffer (e.g., a third page buffer) that amplifies a voltage of a bit line connected to a parity memory cell (formed of a memory cell transistor for ECC processing configured the same as a normal memory cell) and latches the amplified result.” ¶208); and a first sensing circuit electrically coupled to sense signals from memory cells of the first column (“In a conventional semiconductor memory device, a so-called data bus connecting an I/O pad (e.g., an interface unit) and a memory array is formed of a single bus when seen from a sense amplifier (referred to as a page buffer in a flash memory)” ¶310); the first sensing circuit being electrically coupled to provide a first column output to the parity bit input when the memory array is configured for reading a page selected from the first portion of the pages (“The page buffer 102c is a page buffer (e.g., a third page buffer) that amplifies a voltage of a bit line connected to a parity memory cell (formed of a memory cell transistor for ECC processing configured the same as a normal memory cell) and latches the amplified result.” ¶208); and the first sensing circuit being electrically coupled to provide the first column output to the column redundancy bus when the memory array is configured for reading a page selected from the second portion of the pages (“Meanwhile, if a selection signal Sel_B is received from the ECC column coding circuit 108 at a data read operation of the ECC mode, the page buffer 102c outputs the amplified result to the ECC circuit 107 through ECCBus.sub.--1, ECCBus.sub.--2, and ECCBus.sub.--3 as read data Data_Out_B” ¶208).
Regarding claim 3, Miyamoto teaches The memory device of claim 2,
further comprising a second sensing circuit electrically coupled to sense memory cells of a second column of the memory array, the second sensing circuit being electrically coupled to provide a second column output to a data input of the error correction circuit (“The page buffer 102a is a page buffer (e.g., a first page buffer) that amplifies a voltage of a bit line connected to a normal memory cell and latches the amplified result. When the selection signal Sel_A is received from the column coding circuit 103 at a data read operation of a normal mode (e.g., a second mode of operation), the page buffer 102a outputs the amplified result to the I/O pad 106 through DataBus.sub.--1, DataBus.sub.--2, and DataBus.sub.--3 (e.g., a second data bus) as read data Data_Out_A.” ¶205).
Regarding claim 4, Miyamoto teaches The memory device of claim 3,
further comprising a third sensing circuit electrically coupled to sense memory cells of a third column of the memory array, the third sensing circuit being electrically coupled to provide a third column output to the parity bit input of the error correction circuit (“The page buffer 102b operates substantially the same as that of the page buffer 102a, and a description thereof is thus omitted. The column repair circuit 104 is a circuit for replacing a page buffer unit of the page buffer 102a with a page buffer unit of the page buffer 102b.” ¶207).
Regarding claim 5, Miyamoto teaches further comprising a fourth sensing circuit electrically coupled to sense memory cells of a fourth column of the memory array, the fourth sensing circuit being electrically coupled to provide a fourth column output to a second column redundancy bus (“the page buffer 102d is a page buffer (e.g., a fourth page buffer) that is replaced together with a parity memory cell and a bit line when the parity memory cell or the bit line connected to the page buffer 102c is abnormal…. he page buffer 102d operates substantially the same as that of the page buffer 102c” ¶210).
Regarding claim 6, Miyamoto teaches further comprising a multiplexer circuit electrically coupled to selectively direct the first column output to the parity bit input of the error correction circuit or to the column redundancy bus (“The column coding circuit 103 and the ECC column coding circuit 108 output a selection signal Sel_A or a selection signal Sel_B to a PB control circuit 60 of the page buffer 102 to connect an output of a page buffer to either ECCBus.sub.--1 or DataBus.sub.--1 from a portion (e.g., a portion formed of a multiplexer 52.sub.--b and a PB control circuit 83_1 shown in FIG. 22) directly connected to the page buffer 102” ¶201).
Regarding claim 7, Miyamoto teaches The memory device of claim 3,
further comprising a third sensing circuit electrically coupled to sense memory cells of a third column of the memory array, the third sensing circuit being electrically coupled to provide a third column output to the parity bit input of the error correction circuit (“The page buffer 102b operates substantially the same as that of the page buffer 102a, and a description thereof is thus omitted. The column repair circuit 104 is a circuit for replacing a page buffer unit of the page buffer 102a with a page buffer unit of the page buffer 102b.” ¶207); a fourth sensing circuit electrically coupled to sense memory cells of a fourth column of the memory array, the fourth sensing circuit being electrically coupled to provide a fourth column output to a second column redundancy bus (“the page buffer 102d is a page buffer (e.g., a fourth page buffer) that is replaced together with a parity memory cell and a bit line when the parity memory cell or the bit line connected to the page buffer 102c is abnormal…. he page buffer 102d operates substantially the same as that of the page buffer 102c” ¶210);
Regarding claim 8, Miyamoto teaches and a multiplexer circuit electrically coupled to selectively direct the first column output to the parity bit input of the error correction circuit or to the column redundancy bus (“The column coding circuit 103 and the ECC column coding circuit 108 output a selection signal Sel_A or a selection signal Sel_B to a PB control circuit 60 of the page buffer 102 to connect an output of a page buffer to either ECCBus.sub.--1 or DataBus.sub.--1 from a portion (e.g., a portion formed of a multiplexer 52.sub.--b and a PB control circuit 83_1 shown in FIG. 22) directly connected to the page buffer 102” ¶201).
Regarding claim 9, Miyamoto teaches A method of operating a memory device comprising a memory array, the memory array comprising a number of memory cells arranged into a number of pages, (“A plurality of memory cell transistors of the memory array 101 connected to the same word line forms a page. Data is written at and read from memory cell transistors in a page at the same time” ¶72); a number of rows (“Also, the burst read operation is a mode of operation where read data is sequentially output by supplying a column address after driving a word line in response to an active command at the same time with supplying of a row address” ¶500); and a number of columns (“The column coding circuit 83 generates column address signals (Sub BL Coding and Coding shown in FIG. 8) based on a column address to select a page buffer unit in the page buffer 82 corresponding to the column address” ¶78); , with each respective memory cell of the number of memory cells being part of a particular column of the number of columns, a particular row of the number of rows, and a particular page of the number of pages, the method comprising: configuring the memory array for reading a first page of the number of pages; while the memory array is configured for reading the first page, sensing a first column of the number of columns to receive a first column parity output; providing the first column parity output to a parity bit input of an error correction circuit of the memory device; (“A column address is provided to the column coding circuit 103 and the ECC column coding circuit 108. The column coding circuit 103 and the ECC column coding circuit 108 output a selection signal Sel_A or a selection signal Sel_B to a PB control circuit 60 of the page buffer 102 to connect an output of a page buffer to either ECCBus.sub.--1 or DataBus.sub.--1 from a portion (e.g., a portion formed of a multiplexer 52.sub.--b and a PB control circuit 83_1 shown in FIG. 22) directly connected to the page buffer 102” ¶201” ); configuring the memory array for reading a second page of the number of pages; while the memory array is configured for reading the second page, sensing the first column of the number of columns to receive a first column redundancy output; and providing the first column redundancy output to a first column redundancy bus of the memory device (“The page buffer 102c is a page buffer (e.g., a third page buffer) that amplifies a voltage of a bit line connected to a parity memory cell (formed of a memory cell transistor for ECC processing configured the same as a normal memory cell) and latches the amplified result.” ¶208).
Regarding claim 10, Miyamoto teaches further comprising: while the memory array is configured for reading the first page, sensing a second column of the number of columns to receive a second column output for the first page; providing the second column output for the first page to a data input of the error correction circuit; while the memory array is configured for reading the second page, sensing the second column to receive a second column output for the second page; and providing the second column output for the second page to the data input of the error correction circuit (“The page buffer 102a is a page buffer (e.g., a first page buffer) that amplifies a voltage of a bit line connected to a normal memory cell and latches the amplified result. When the selection signal Sel_A is received from the column coding circuit 103 at a data read operation of a normal mode (e.g., a second mode of operation), the page buffer 102a outputs the amplified result to the I/O pad 106 through DataBus.sub.--1, DataBus.sub.--2, and DataBus.sub.--3 (e.g., a second data bus) as read data Data_Out_A.” ¶205).
Regarding claim 11, Miyamoto teaches wherein the first column is configured to store parity data for a first portion of the number of pages and column redundancy data for a second portion of the number of pages, the first portion of the number of pages comprising the first page and the second portion of the number of pages comprising the second page (“Meanwhile, if the selection signal Sel_B is received from the ECC column coding circuit 108 at a data write operation of the ECC mode, the page buffer 102c receives parity data being a result of ECC processing of the ECC circuit 107 through ECCBus.sub.--3, ECCBus.sub.--2, and ECCBus.sub.--1 as write data Data_Out_B” ¶209).
Regarding claim 12, Miyamoto teaches sensing a third column of the number of columns to receive a third column output; and providing the third column output to the parity bit input of the error correction circuit (“the page buffer 102d is a page buffer (e.g., a fourth page buffer) that is replaced together with a parity memory cell and a bit line when the parity memory cell or the bit line connected to the page buffer 102c is abnormal…. he page buffer 102d operates substantially the same as that of the page buffer 102c” ¶210).
Regarding claim 13, Miyamoto teaches while the memory array is configured for reading the first page, sensing a third column of the number of columns to receive a third column output for the first page; providing the third column output for the first page to a second column redundancy bus of the memory device (“a first repair circuit that is connected to the second bus and repairs a page buffer, connected to a defective memory cell or bit line, from among the first page buffer with the second page buffer, a second repair circuit that is connected to the first bus and repairs a page buffer, connected to a defective memory cell or bit line, from among the third page buffer with the fourth page buffer, and an ECC circuit that is connected to the first data bus and corrects an error of output data of the first and second page buffers based on output data of the third and fourth page buffers” ¶193 ); while the memory array is configured for reading the second page, sensing the third column to receive a third column output for the second page; and providing the third column output for the second page to the second column redundancy bus of the memory device (“The page buffer 102c is a page buffer (e.g., a third page buffer) that amplifies a voltage of a bit line connected to a parity memory cell (formed of a memory cell transistor for ECC processing configured the same as a normal memory cell) and latches the amplified result.” ¶208 );
Regarding claim 14, Miyamoto teaches the providing of the first column parity output to the parity bit input of the error correction circuit comprising configuring a multiplexer to direct an output of the first column to the parity bit input of the error correction circuit (“The column coding circuit 103 and the ECC column coding circuit 108 output a selection signal Sel_A or a selection signal Sel_B to a PB control circuit 60 of the page buffer 102 to connect an output of a page buffer to either ECCBus.sub.--1 or DataBus.sub.--1 from a portion (e.g., a portion formed of a multiplexer 52.sub.--b and a PB control circuit 83_1 shown in FIG. 22) directly connected to the page buffer 102” ¶201).
Regarding claim 15, Miyamoto teaches further comprising modifying a second column multiplexer associated with a second column of the number of columns to direct the first column parity output from the first column redundancy bus to a data input of the error correction circuit associated with the second column (“a main column repair multiplexer (a column repair circuit) 104, a parity column repair circuit (Parity CRMUX) 105,” ¶200)
Regarding claim 16, Miyamoto teaches further comprising: receiving first write data for writing to the first page of the number of pages; determining first parity data for the first write data; writing the first parity data to the first column; writing the first write data to at least one other column of the number of columns; receiving second write data for writing to a second page of the number of pages; and writing at least a portion of the second write data to a portion to the first column (“If the selection signal Sel_A is received from the column coding circuit 103 at a data write operation of the normal mode, the page buffer 102a receives, as write data Data_In_A, write data through DataBus.sub.--3, DataBus.sub.--2, and DataBus.sub.--1. If the selection signal Sel_B is received from the ECC column coding circuit 108 at a data write operation of the ECC mode, the page buffer 102a receives, as write data Data_In_B, a result of ECC processing through ECCBus.sub.--3, ECCBus.sub.--2, and ECCBus.sub.—1” ¶206).
Regarding claim 17, Miyamoto teaches A memory device comprising: an error correction circuit; a memory array comprising a number of memory cells arranged into a number of pages, (“A plurality of memory cell transistors of the memory array 101 connected to the same word line forms a page. Data is written at and read from memory cell transistors in a page at the same time” ¶72); a number of rows (“Also, the burst read operation is a mode of operation where read data is sequentially output by supplying a column address after driving a word line in response to an active command at the same time with supplying of a row address” ¶500); and a number of columns (“The column coding circuit 83 generates column address signals (Sub BL Coding and Coding shown in FIG. 8) based on a column address to select a page buffer unit in the page buffer 82 corresponding to the column address” ¶78); a row of the number of rows, and a page of the number of pages; means for configuring the memory array for reading a selected page of the number of pages; means for sensing memory cells of a first column of the number of columns; and means for providing a first column output to a parity bit input of the error correction circuit when the memory array is configured for reading a page selected from a first portion of the number of pages, (“A column address is provided to the column coding circuit 103 and the ECC column coding circuit 108. The column coding circuit 103 and the ECC column coding circuit 108 output a selection signal Sel_A or a selection signal Sel_B to a PB control circuit 60 of the page buffer 102 to connect an output of a page buffer to either ECCBus.sub.--1 or DataBus.sub.--1 from a portion (e.g., a portion formed of a multiplexer 52.sub.--b and a PB control circuit 83_1 shown in FIG. 22) directly connected to the page buffer 102” ¶201” ); configuring the memory array for reading a second page of the number of pages; while the memory array is configured for reading the second page, sensing the first column of the number of columns to receive a first column redundancy output; and providing the first column redundancy output to a first column redundancy bus of the memory device (“The page buffer 102c is a page buffer (e.g., a third page buffer) that amplifies a voltage of a bit line connected to a parity memory cell (formed of a memory cell transistor for ECC processing configured the same as a normal memory cell) and latches the amplified result.” ¶208). “Means for” is interpreted as respective circuits that perform these operations as described in applicant’s specification, for example in paragraph 41, “The sensing circuits may comprise various amplifiers, analog-to-digital converters, multiplexers, and/or the like.”.
Regarding claim 18, Miyamoto teaches further comprising: means for sensing memory cells of a second column of the number of columns; and means for providing a second column output to a data input of the error correction circuit (“The page buffer 102a is a page buffer (e.g., a first page buffer) that amplifies a voltage of a bit line connected to a normal memory cell and latches the amplified result. When the selection signal Sel_A is received from the column coding circuit 103 at a data read operation of a normal mode (e.g., a second mode of operation), the page buffer 102a outputs the amplified result to the I/O pad 106 through DataBus.sub.--1, DataBus.sub.--2, and DataBus.sub.--3 (e.g., a second data bus) as read data Data_Out_A.” ¶205).
Regarding claim 19, Miyamoto teaches further comprising: means for sensing memory cells of a third column of the number of columns; and means for providing a third column output to the parity bit input of the error correction circuit (“The page buffer 102b operates substantially the same as that of the page buffer 102a, and a description thereof is thus omitted. The column repair circuit 104 is a circuit for replacing a page buffer unit of the page buffer 102a with a page buffer unit of the page buffer 102b.” ¶207).
Regarding claim 20, Miyamoto teaches further comprising: means for sensing memory cells of a fourth column of the number of columns; and means for providing a fourth column output to a second column redundancy bus (“the page buffer 102d is a page buffer (e.g., a fourth page buffer) that is replaced together with a parity memory cell and a bit line when the parity memory cell or the bit line connected to the page buffer 102c is abnormal…. he page buffer 102d operates substantially the same as that of the page buffer 102c” ¶210).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN KEVIN MCNAMARA whose telephone number is (703)756-1884. The examiner can normally be reached Monday-Friday 7:30-5:00 EST.
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/SEAN KEVIN MCNAMARA/Examiner, Art Unit 2113
/PHILIP GUYTON/Primary Examiner, Art Unit 2113
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