Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 19 of U.S. Patent No. 12,355,460.
. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the issued patents make obvious the claims of the pending application in that the limitations claimed in the pending application are found in the issued patents even though they are not necessarily presented in the same order as those in the issued patents. “A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the issued patent make obvious the claims of the pending application in that the limitations claimed in the pending application are similarly claimed in the issued patents and the claims are directed to substantially the same subject matter as the parent case though not necessarily presented in the same sequential order or the same claim numbering as shown in the table below
US Application Number 19/214,148
US Patent Number 12,355,460
(Claim 1)
An analog-to-digital converter, comprising: a voltage-to-delay circuit having a voltage input and first and second outputs; a plurality of residue stages coupled in a sequence, comprising: a first residue stage, having a first input coupled to the first output of the voltage-to-delay circuit, a second input coupled to the second output of the voltage-to- delay circuit, a sign bit output presenting a signal indicating a polarity of a relative delay between transitions at of the first and second outputs of the voltage-to-delay circuit, and first and second residue outputs; and a second residue stage coupled to the first residue stage, and comprising: a logic gate having a first input coupled to the first residue output, a second input coupled to the second residue output, and a first residue output; and a delay comparator having a first input, a second input, a sign bit output, and a second residue output; and digital circuitry having inputs coupled to the outputs of the first residue stage and each of the plurality of residue stages, and having one or more calibration outputs coupled to the residue stage; wherein the delay comparator comprises: a time-domain comparator configured to generate a differential voltage responsive to a delay between signals at the first and second inputs of the delay comparator; a voltage barrier coupled to receive the differential voltage from the time-domain comparator, and having first and second intermediate outputs; an output stage, comprising a first transistor having a conductive path coupled between a bias voltage and the second residue output and having a control terminal coupled to the first intermediate output of the voltage barrier, and a second transistor having a conductive path coupled between the bias voltage and the second residue output and having a control terminal coupled to the second intermediate output of the voltage barrier; a first trim circuit coupled to the first intermediate output of the voltage barrier, and an input coupled to the digital circuitry; and a second trim circuit coupled to the first intermediate output of the voltage barrier, and an input coupled to the digital circuitry.
(Claim 1)
An analog-to-digital converter, comprising: a voltage-to-delay circuit having a voltage input and first and second outputs; a plurality of residue stages coupled in a sequence, comprising: a first residue stage, having a first input coupled to the first output of the voltage-to-delay circuit, a second input coupled to the second output of the voltage-to-delay circuit, a sign bit output presenting a signal indicating a polarity of a relative delay between transitions at of the first and second outputs of the voltage-to-delay circuit, and first and second residue outputs; and a second residue stage coupled to the first residue stage, and comprising: a logic gate having a first input coupled to the first residue output, a second input coupled to the second residue output, and a first residue output; and a delay comparator having a first input, a second input, a sign bit output, and a second residue output; and digital circuitry having inputs coupled to the outputs of the plurality of residue stages, and having one or more calibration outputs coupled to one or more residue stages; wherein the delay comparator comprises: a time-domain comparator configured to generate a differential voltage responsive to a delay between signals at the first and second inputs of the delay comparator; a voltage circuit coupled to receive the differential voltage from the time-domain comparator, and having first and second intermediate outputs; an output stage, comprising a first transistor having a conductive path coupled between a bias voltage and the second residue output and having a control terminal coupled to the first intermediate output of the voltage circuit, and a second transistor having a conductive path coupled between the bias voltage and the second residue output and having a control terminal coupled to the second intermediate output of the voltage circuit; a first trim circuit coupled to the first intermediate output of the voltage circuit, and an input coupled to the digital circuitry; and a second trim circuit coupled to the second intermediate output of the voltage circuit, and an input coupled to the digital circuitry.
(Claim 2)
The analog-to-digital converter of claim 1, wherein each of the first and second trim circuits comprises a variable capacitor configurable to a selected capacitance responsive to a calibration signal from the digital circuitry.
(Claim 2)
The analog-to-digital converter of claim 1, wherein each of the first and second trim circuits comprises a variable capacitor configurable to a selected capacitance responsive to a calibration signal from the digital circuitry.
(Claim 3). The analog-to-digital converter of claim 2, further comprising: a digital-to-analog converter, having an input coupled to the digital circuitry and an analog output; an input multiplexer having a first input coupled to receive an input voltage, a second input coupled to the analog output of the digital-to-analog converter, a control input coupled to the digital circuitry, and an output coupled to the voltage input of the voltage to delay circuit; wherein the digital circuitry is configured to apply, in a calibration mode, a selected calibration voltage to the digital-to-analog circuitry and a control signal to the input multiplexer to select the analog output of the digital-to-analog converter.
(Claim 3The analog-to-digital converter of claim 2, further comprising: a digital-to-analog converter, having an input coupled to the digital circuitry and an analog output; and an input multiplexer having a first input coupled to receive an input voltage, a second input coupled to the analog output of the digital-to-analog converter, a control input coupled to the digital circuitry, and an output coupled to the voltage input of the voltage to delay circuit; wherein the digital circuitry is configured to apply, in a calibration mode, a selected calibration voltage to the digital-to-analog converter and a control signal to the input multiplexer to select the analog output of the digital-to-analog converter.
(Claim 4)
The analog-to-digital converter of claim 3, wherein the digital circuitry is configured to, in the calibration mode, apply a calibration signal to the first trim circuit of the second residue stage for a selected calibration voltage in a first voltage range, and apply a calibration signal to the second trim circuit of the of the second residue stage for a selected calibration voltage in a second voltage range.
(Claim 4)
The analog-to-digital converter of claim 3, wherein the digital circuitry is configured to, in the calibration mode, apply a calibration signal to the first trim circuit of the second residue stage for a selected calibration voltage in a first voltage range, and apply a calibration signal to the second trim circuit of the of the second residue stage for a selected calibration voltage in a second voltage range.
(Claim 5)
The analog-to-digital converter of claim 3, wherein the second residue stage further comprises: a third trim circuit coupled to the logic gate, the third trim circuit having an input coupled to the digital circuitry.
(Claim 5)
The analog-to-digital converter of claim 3, wherein the second residue stage further comprises: a third trim circuit coupled to the logic gate, the third trim circuit having an input coupled to the digital circuitry.
(Claim 6)
The analog-to-digital converter of claim 1, wherein the first residue stage has a plurality of sign bit outputs presenting a plurality of sign bits to the digital circuitry responsive to the delay magnitude of the first and second outputs of the voltage to delay circuit.
(Claim 6)
The analog-to-digital converter of claim 1, wherein the first residue stage has a plurality of sign bit outputs presenting a plurality of sign bits to the digital circuitry responsive to the delay magnitude of the first and second outputs of the voltage to delay circuit.
(Claim 7)
The analog-to-digital converter of claim 1, wherein the plurality of residue stages further comprises a third residue stage, the third residue stage comprising: a logic gate having a first input coupled to a first residue output of the second residue stage, a second input coupled to the second residue output of the second residue stage, and a first residue output; and a delay comparator having a first input coupled to a first residue output of the second residue stage, a second input coupled to the second residue output of the second residue stage, a sign bit output, and a second residue output, the delay comparator comprising: a time-domain comparator configured to generate a differential voltage responsive to a delay between signals at the first and second inputs of the delay comparator; a voltage barrier coupled to receive the differential voltage from the time-domain comparator, and having first and second intermediate outputs; an output stage, comprising a first transistor having a conductive path coupled between a bias voltage and the second residue output and having a control terminal coupled to the first intermediate output of the voltage barrier, and a second transistor having a conductive path coupled between the bias voltage and the second residue output and having a control terminal coupled to the second intermediate output of the voltage barrier; a first trim circuit coupled to the first intermediate output of the voltage barrier, and comprising: a first variable capacitor configurable to a selected capacitance responsive to a calibration signal from the digital circuitry; a second variable capacitor configurable to a selected capacitance responsive to a calibration signal from the digital circuitry; and a first select circuit, coupled to a previous residue stage in the sequence, and configured to couple the first variable capacitor to the first intermediate output if the digital output of the previous residue stage is at a first logic level, and to couple the second variable capacitor to the first intermediate output if the digital output of the previous residue stage is at a second logic level; and a second trim circuit coupled to the second intermediate output of the voltage barrier, and comprising: a third variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; a fourth variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; and a second select circuit, coupled to a previous residue stage in the sequence, and configured to couple the third variable capacitor to the second intermediate output if the digital output of the previous residue stage is at the first logic level, and to couple the fourth variable capacitor to the second intermediate output if the digital output of the previous residue stage is at the second logic level.
(Claim 7)
The analog-to-digital converter of claim 1, wherein the plurality of residue stages further comprises a third residue stage, the third residue stage comprising: a logic gate having a first input coupled to a first residue output of the second residue stage, a second input coupled to the second residue output of the second residue stage, and a first residue output; and a delay comparator having a first input coupled to a first residue output of the second residue stage, a second input coupled to the second residue output of the second residue stage, a sign bit output, and a second residue output, the delay comparator comprising: a time-domain comparator configured to generate a differential voltage responsive to a delay between signals at the first and second inputs of the delay comparator; a voltage circuit coupled to receive the differential voltage from the time-domain comparator, and having first and second intermediate outputs; an output stage, comprising a first transistor having a conductive path coupled between a bias voltage and the second residue output and having a control terminal coupled to the first intermediate output of the voltage circuit, and a second transistor having a conductive path coupled between the bias voltage and the second residue output and having a control terminal coupled to the second intermediate output of the voltage circuit; a first trim circuit coupled to the first intermediate output of the voltage circuit, and comprising: a first variable capacitor configurable to a selected capacitance responsive to a calibration signal from the digital circuitry; a second variable capacitor configurable to a selected capacitance responsive to a calibration signal from the digital circuitry; and a first select circuit, coupled to a previous residue stage in the sequence, and configured to couple the first variable capacitor to the first intermediate output if the digital output of the previous residue stage is at a first logic level, and to couple the second variable capacitor to the first intermediate output if the digital output of the previous residue stage is at a second logic level; and a second trim circuit coupled to the second intermediate output of the voltage circuit, and comprising: a third variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; a fourth variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; and a second select circuit, coupled to a previous residue stage in the sequence, and configured to couple the third variable capacitor to the second intermediate output if the digital output of the previous residue stage is at the first logic level, and to couple the fourth variable capacitor to the second intermediate output if the digital output of the previous residue stage is at the second logic level.
(Claim 8)
A method of calibrating an analog-to-digital converter, the method comprising: causing a voltage-to-delay device to generate a delay signal based on a calibration voltage; at a first residue stage; receiving the delay signal at an input: generating a sign bit based on the delay signal; and providing a residue delay signal based on the delay signal to an input of a successive residue stage; at each of a plurality of successive residue stages: generating a sign bit based on the residue delay signal at its input; and providing a residue delay signal to an input of a next successive residue stage, based on the residue signal at its input; and adjusting one or more of the successive residue stages, the adjusting step comprising: adjusting a first response of the residue stage at a first intermediate output for a calibration voltage in a first range; and adjusting a second response of the residue stage at a second intermediate output for a calibration voltage in a second range.
(Claim 8)
A method of calibrating an analog-to-digital converter, the method comprising: causing a voltage-to-delay device to generate a delay signal based on a calibration voltage; at a first residue stage; receiving the delay signal at an input: generating a sign bit based on the delay signal; and generating a residue delay signal based on the delay signal; at each of a plurality of successive residue stages: generating a sign bit based on the residue delay signal at its input; and providing a residue delay signal to an input of a next successive residue stage, based on the residue delay signal at its input; and adjusting one or more of the successive residue stages, the adjusting step comprising: adjusting a first response of the residue stage at a first intermediate output for a calibration voltage in a first range; and adjusting a second response of the residue stage at a second intermediate output for a calibration voltage in a second range.
(Claim 9)
The method of claim 8, wherein the residue delay signal at an output of a residue stage is a delay between transitions at first and second outputs of the residue stage; and wherein the step of providing a residue delay signal at each of the successive delay-based stages comprises: applying a logic function response to transitions at the first and second outputs of a previous residue stage to produce a transition at a first residue output; and generating a differential voltage responsive to a delay between the transitions at the first and second outputs of the previous residue stage; at a voltage barrier circuit, driving an output voltage at one of the first and second intermediate outputs responsive to the differential voltage; and driving a second residue output responsive to the driving of the output voltage at one of the first and second delay comparator nodes; wherein the step of adjusting the first delay comprises adjusting a first variable capacitance coupled to the first intermediate output for a calibration voltage in the first range; and wherein the step of adjusting the second delay comprises adjusting a second variable capacitance coupled to the second intermediate output for a calibration voltage signal in the second range.
(Claim 9)
The method of claim 8, wherein the residue delay signal at an output of a residue stage is a delay between transitions at first and second outputs of the residue stage; and wherein the step of providing a residue delay signal at each of the successive delay-based stages comprises: applying a logic function response to transitions at the first and second outputs of a previous residue stage to produce a transition at a first residue output; and generating a differential voltage responsive to a delay between the transitions at the first and second outputs of the previous residue stage; at a voltage circuit, driving an output voltage at one of the first and second intermediate outputs responsive to the differential voltage; and driving a second residue output responsive to the driving of the output voltage at one of the first and second delay comparator nodes; wherein the step of adjusting the first delay comprises adjusting a first variable capacitance coupled to the first intermediate output for a calibration voltage in the first range; and wherein the step of adjusting the second delay comprises adjusting a second variable capacitance coupled to the second intermediate output for a calibration voltage signal in the second range.
(Claim 10)
. The method of claim 9, wherein the adjusting step further comprises: adjusting a delay in the logic function for a calibration voltage.
(Claim 10)
The method of claim 9, wherein the adjusting step further comprises: adjusting a delay in the logic function for a calibration voltage.
(Claim 11)
The method of claim 9, wherein the at least one of the successive residue stages is at least a second one in a sequence of the successive delay-based stages; wherein the step of adjusting the first delay comprises: adjusting the first variable capacitance coupled to the first intermediate output for the calibration voltage in the first range in combination if the sign bit from a previous residue stage is at a first logic level; and adjusting a third variable capacitance coupled to the first intermediate output for the calibration voltage in the first range in combination if the sign bit from a previous residue stage is at a second logic level; and wherein the step of adjusting the second delay comprises: adjusting the second variable capacitance coupled to the second intermediate output for the calibration voltage in the second range in combination if the sign bit from a previous residue stage is at the first logic level; and adjusting a fourth variable capacitance coupled to the second delay intermediate output for the calibration voltage in the second range in combination if the sign bit from a previous residue stage is at the second logic level.
(Claim 11)
The method of claim 9, wherein the at least one of the successive residue stages is at least a second one in a sequence of the successive delay-based stages; wherein the step of adjusting the first delay comprises: adjusting the first variable capacitance coupled to the first intermediate output for the calibration voltage in the first range in combination if the sign bit from a previous residue stage is at a first logic level; and adjusting a third variable capacitance coupled to the first intermediate output for the calibration voltage in the first range in combination if the sign bit from a previous residue stage is at a second logic level; and wherein the step of adjusting the second delay comprises: adjusting the second variable capacitance coupled to the second intermediate output for the calibration voltage in the second range in combination if the sign bit from a previous residue stage is at the first logic level; and adjusting a fourth variable capacitance coupled to the second intermediate output for the calibration voltage in the second range in combination if the sign bit from a previous residue stage is at the second logic level.
(Claim 12)
The method of claim 8, wherein the step of generating a digital signal at the first delay-based stage comprises generating a multi-bit digital signal.
(Claim 12)
The method of claim 8, wherein the step of generating a digital signal at the first delay-based stage comprises generating a multi-bit digital signal.
(Claim 13)
An analog-to-digital converter, comprising: a voltage-to-delay circuit having a voltage input, and configured to generate signals at first and second outputs having a relative delay magnitude corresponding to a voltage at the voltage input; a plurality of residue stages coupled in a sequence, comprising: a first residue stage, having a first input coupled to the first output of the voltage-to-delay circuit, a second input coupled to the second output of the voltage-to- delay circuit, one or more digital outputs presenting one or more bits responsive to the delay magnitude of the first and second outputs of the voltage-to-delay circuit, and first and second outputs presenting delay signals corresponding to a residue; one or more residue stages coupled in the sequence with the first residue stage, each residue stage comprising: a logic gate having a first input coupled to the first output of the previous residue stage in the sequence, a second input coupled to the second output of the previous residue stage in the sequence, and a first residue output; and a delay comparator having a first input coupled to the first output of the previous residue stage in the sequence, a second input coupled to the second output of the previous residue stage in the sequence, a sign bit output, and a second residue output; digital circuitry having inputs coupled to the digital outputs of the first residue stage and the sign bit output of each of the plurality of residue stages, and having one or more calibration outputs coupled to at least one of the residue stages; a digital-to-analog converter, having an input coupled to the digital circuitry and an analog output; an input multiplexer having a first input coupled to receive an input voltage, a second input coupled to the analog output of the digital-to-analog converter, a control input coupled to the digital circuitry, and an output coupled to the voltage input of the voltage-to-delay circuit; wherein the digital circuitry is configured to apply, in a calibration mode, a selected calibration voltage to the digital-to-analog circuitry and a control signal to the input multiplexer to select the analog output of the digital-to-analog converter; wherein the delay comparator of the at least one of the residue stages coupled to calibration outputs of the digital circuitry comprises first and second trim circuits coupled to first and second intermediate nodes, each of the first and second trim circuits coupled to receive calibration signals from the digital circuitry in the calibration mode.
(Claim 13)
An analog-to-digital converter, comprising: a voltage-to-delay circuit having a voltage input, and configured to generate signals at first and second outputs having a relative delay magnitude corresponding to a voltage at the voltage input; a plurality of residue stages coupled in a sequence, comprising: a first residue stage, having a first input coupled to the first output of the voltage-to-delay circuit, a second input coupled to the second output of the voltage-to-delay circuit, one or more digital outputs presenting one or more bits responsive to the delay magnitude of the first and second outputs of the voltage-to-delay circuit, and first and second outputs presenting delay signals corresponding to a residue; one or more residue stages coupled in the sequence with the first residue stage, each residue stage comprising: a logic gate having a first input coupled to the first output of a previous residue stage in the sequence, a second input coupled to the second output of the previous residue stage in the sequence, and a first residue output; and a delay comparator having a first input coupled to the first output of the previous residue stage in the sequence, a second input coupled to the second output of the previous residue stage in the sequence, a sign bit output, and a second residue output; digital circuitry having inputs coupled to the digital outputs of the first residue stage and the sign bit output of each of the plurality of residue stages, and having one or more calibration outputs coupled to at least one of the residue stages; a digital-to-analog converter, having an input coupled to the digital circuitry and an analog output; and an input multiplexer having a first input coupled to receive an input voltage, a second input coupled to the analog output of the digital-to-analog converter, a control input coupled to the digital circuitry, and an output coupled to the voltage input of the voltage-to-delay circuit; wherein the digital circuitry is configured to apply, in a calibration mode, a selected calibration voltage to the digital-to-analog converter and a control signal to the input multiplexer to select the analog output of the digital-to-analog converter; wherein the delay comparator of the at least one of the residue stages coupled to calibration outputs of the digital circuitry comprises first and second trim circuits coupled to first and second intermediate nodes, each of the first and second trim circuits coupled to receive calibration signals from the digital circuitry in the calibration mode.
(Claim 14)
The analog-to-digital converter of claim 13, wherein the digital circuitry is configured to, in the calibration mode, apply a first calibration signal to the first trim circuit of the at least one of the residue stages for a selected calibration voltage in a first voltage range, and apply a second calibration signal to the second trim circuit of the of the at least one of the residue stages for a selected calibration voltage in a second voltage range.
(Claim 14)
The analog-to-digital converter of claim 13, wherein the digital circuitry is configured to, in the calibration mode, apply a first calibration signal to the first trim circuit of the at least one of the residue stages for a selected calibration voltage in a first voltage range, and apply a second calibration signal to the second trim circuit of the at least one of the residue stages for a selected calibration voltage in a second voltage range.
(Claim 15)
. The analog-to-digital converter of claim 14, wherein the delay comparator of the at least one of the residue stages comprises: time-domain comparator circuitry configured to generate a differential voltage responsive to a delay between signals at the first and second inputs of the delay comparator; a voltage barrier circuit configured to drive a voltage at one of first and second intermediate outputs responsive to the differential voltage from the time- domain comparator circuitry; an output stage, coupled to the first and second intermediate outputs, and configured to drive the second residue output responsive to the voltage driven at one of the first and second intermediate nodes
(Claim 15)
The analog-to-digital converter of claim 14, wherein the delay comparator of the at least one of the residue stages comprises: time-domain comparator circuitry configured to generate a differential voltage responsive to a delay between signals at the first and second inputs of the delay comparator; a voltage circuit configured to drive a voltage at one of first and second intermediate outputs responsive to the differential voltage from the time-domain comparator circuitry; and an output stage, coupled to the first and second intermediate outputs, and configured to drive the second residue output responsive to the voltage driven at one of the first and second intermediate nodes.
(Claim 16)
The analog-to-digital converter of claim 9, wherein each of the first and second trim circuits comprises a variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry.
(Claim 16)
The analog-to-digital converter of claim 13, wherein each of the first and second trim circuits comprises a variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry.
(Claim 17)
. The analog-to-digital converter of claim 9, wherein each of the residue stages following the at least one residue stage further comprises: a third trim circuit coupled to the logic gate, the third trim circuit having an input coupled to a calibration output of the digital circuitry.
(Claim 17)
The analog-to-digital converter of claim 16, wherein each of the residue stages following the at least one residue stage further comprises: a third trim circuit coupled to the logic gate, the third trim circuit having an input coupled to a calibration output of the digital circuitry.
(Claim 18)
The analog-to-digital converter of claim 9, wherein the at least one of the residue stages coupled to calibration outputs of the digital circuitry is the third or subsequent residue stage in the sequence; wherein the first trim circuit comprises: a first variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; a second variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; and a first select circuit, coupled to a previous residue stage in the sequence, and configured to couple the first variable capacitor to the first intermediate node if the sign bit output of the previous residue stage is at a first logic level, and to couple the second variable capacitor to the first intermediate node if the sign bit output of the previous residue stage is at a second logic level; and wherein the second trim circuit comprises: a third variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; a fourth variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; and a second select circuit, coupled to a previous residue stage in the sequence, and configured to couple the third variable capacitor to the second intermediate node if the sign bit output of the previous residue stage is at the first logic level, and to couple the fourth variable capacitor to the second intermediate node if the sign bit output of the previous residue stage is at the second logic level.
(Claim 18)
The analog-to-digital converter of claim 16, wherein the at least one of the residue stages coupled to calibration outputs of the digital circuitry is a third or subsequent residue stage in the sequence; wherein the first trim circuit comprises: a first variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; a second variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; and a first select circuit, coupled to a previous residue stage in the sequence, and configured to couple the first variable capacitor to the first intermediate node if the sign bit output of the previous residue stage is at a first logic level, and to couple the second variable capacitor to the first intermediate node if the sign bit output of the previous residue stage is at a second logic level; and wherein the second trim circuit comprises: a third variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; a fourth variable capacitor configurable to a selected capacitance responsive to a calibration signal from a calibration output of the digital circuitry; and a second select circuit, coupled to a previous residue stage in the sequence, and configured to couple the third variable capacitor to the second intermediate node if the sign bit output of the previous residue stage is at the first logic level, and to couple the fourth variable capacitor to the second intermediate node if the sign bit output of the previous residue stage is at the second logic level.
(Claim 19)
The analog-to-digital converter of claim 18, wherein each of the residue stages following the at least one residue stage further comprises: a third trim circuit coupled to the logic gate, the third trim circuit having an input coupled to a calibration output of the digital circuitry.
(Claim 19)
The analog-to-digital converter of claim 18, wherein each of the residue stages following the at least one residue stage further comprises: a third trim circuit coupled to the logic gate, the third trim circuit having an input coupled to a calibration output of the digital circuitry.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
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