DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 21 May 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figure 4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 13-16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2023/0238040) in view of Concordel (US 5,359,694).
In regards to claim 1, Ryu teaches a storage device comprising:
a first package (first memory package 50-1, figure 3) including first dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061);
a second package (second memory package 50-2, figure 3) including second dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061);
a first chip enable (CE) signal line connected in common to the first and second packages (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046);
a first command signal line connected in common to the first and second packages (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046); and
a controller (memory controller 200, figure 3) configured to
select one die of dies included in packages connected in common to the first CE signal line by applying a CE signal to the first CE signal line and a chip enable reduction (CER) command signal to the first command signal line (“In accordance with an embodiment of the present disclosure, the storage device 1000 may address a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal in the addressing of the memory die.”, paragraph 0120; “In accordance with an embodiment of the present disclosure, the storage device 1000 may address the memory die by further using a data (DQ) signal input during the predetermined N cycles, where N is a natural number.”, paragraph 0125),
wherein the CER command signal includes
at least one package identification bit for package selection (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among a plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during at least one cycle, in the addressing of the memory die.”, paragraph 0121) and
at least one die identification bit for die selection (“In accordance with an embodiment of the present disclosure, the storage device 1000 may address the memory die by further using a data (DQ) signal input during the predetermined N cycles, where N is a natural number.”, paragraph 0125).
Ryu fails to teach that each of the first and second packages includes at least one identification pin,
the at least one identification pin applied with at least one package identification voltage respectively corresponding to the at least one package identification bit.
Concordel teaches that each of the first and second packages includes at least one identification pin (“For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 51-56),
the at least one identification pin applied with at least one package identification voltage respectively corresponding to the at least one package identification bit (“For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip). In such embodiments, the chip compares selected bits of each address that it generate (for example, the two most significant bits of each address) with the locally available package identification data, and processes a given part of an input image data strip only if the compared bits match the locally available package identification data.”, Col. 9, lines 51-62)
thereby “distinguishing it from other identical chips” (Col. 9, line 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel such that each of the first and second packages includes at least one identification pin,
the at least one identification pin applied with at least one package identification voltage respectively corresponding to the at least one package identification bit
thereby “distinguishing it from other identical chips” (id.).
In regards to claim 4, Concordel further teaches that the at least one package identification voltage includes two different voltage levels applied from outside of the first and second packages (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded. For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 47-56), and
each of the at least one identification pin is configured to have one voltage level of the two different voltage levels (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded. For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 47-56).
In regards to claim 5, Concordel further teaches that the at least one package identification bit includes a bit value differently set for each package (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded.”, Col. 9, lines 47-51), and
each of the at least one package identification voltage includes a voltage level corresponding to a bit value of each of the at least one package identification bit corresponding to a relevant package (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded. For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 47-56).
In regards to claim 13, Ryu further teaches that the CER command signal includes one package identification bit (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among a plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during at least one cycle, in the addressing of the memory die.”, paragraph 0121), and
the controller selects one die of the first dies and the second dies based on the CE signal and the CER command signal (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among a plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during at least one cycle, in the addressing of the memory die.”, paragraph 0121).
Concordel further teaches that each of the first and second packages includes one identification pin to which one identification voltage corresponding to the one package identification bit is applied (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded. For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 47-56).
In regards to claim 14, Ryu further teaches a third package (third memory package 50-3, figure 3) including third dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061); and
a fourth package (fourth memory package 50-4, figure 3) including fourth dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061),
wherein each of the first CE signal line and the first command signal line is connected in common to the first to fourth packages (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
the CER command signal includes two package identification bits (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among a plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during at least one cycle, in the addressing of the memory die.”, paragraph 0121), and
the controller is configured to select one die of the first dies to fourth dies based on the CE signal and the CER command signal (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among the plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during a first cycle, further address an interface among the plurality of interfaces by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during a second cycle, and further address a memory die group among the plurality of memory die groups by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during a third cycle, in the addressing of the memory die.”, paragraph 0124).
Concordel further teaches that each of the first to fourth packages includes two identification pins applied with two package identification voltages respectively corresponding to the two package identification bits (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded. For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 47-56).
In regards to claim 15, Ryu further teaches a third package (third memory package 50-3, figure 3) including third dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061);
a fourth package (fourth memory package 50-4, figure 3) including fourth dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061);
a fifth package (“Also, although a form in which four memory packages are included in one package group is illustrated in FIG. 3, the present disclosure may be implemented with a larger number of memory packages.”, paragraph 0058) including fifth dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061);
a sixth package (“Also, although a form in which four memory packages are included in one package group is illustrated in FIG. 3, the present disclosure may be implemented with a larger number of memory packages.”, paragraph 0058) including sixth dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061);
a seventh package (“Also, although a form in which four memory packages are included in one package group is illustrated in FIG. 3, the present disclosure may be implemented with a larger number of memory packages.”, paragraph 0058) including seventh dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061); and
an eighth package (“Also, although a form in which four memory packages are included in one package group is illustrated in FIG. 3, the present disclosure may be implemented with a larger number of memory packages.”, paragraph 0058) including eighth dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061),
wherein each of the first CE signal line and the first command signal line is connected in common to the first to eighth packages (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
wherein the CER command signal includes three package identification bits (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among a plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during at least one cycle, in the addressing of the memory die.”, paragraph 0121), and
the controller is configured to select one die of the first dies to eighth dies based on the CE signal and the CER command signal (“In accordance with an embodiment of the present disclosure, the storage device 1000 may further address a memory package among the plurality of memory packages by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during a first cycle, further address an interface among the plurality of interfaces by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during a second cycle, and further address a memory die group among the plurality of memory die groups by using the address latch enable (ALE) signal and the command latch enable (CLE) signal, which are input during a third cycle, in the addressing of the memory die.”, paragraph 0124).
Concordel further teaches that each of the first to eighth packages includes three identification pins applied with three package identification voltages respectively corresponding to the three package identification bits (“Optionally, the chip of FIG. 6 (or FIG. 7) is provided with package identification data (which will preferably comprise two bits, but which can comprise more than two bits) distinguishing it from other identical chips with which it may be cascaded. For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip).”, Col. 9, lines 47-56).
In regards to claim 16, Ryu further teaches that the first dies are among a plurality of first package dies included in the first package (“Referring to FIG. 4, the memory package 50 may include a first die group 51, a second die group 52, and an interface 53.”, paragraph 0060), and
the second dies are among a plurality of second package dies included in the second package (“Referring to FIG. 4, the memory package 50 may include a first die group 51, a second die group 52, and an interface 53.”, paragraph 0060).
In regards to claim 18, Ryu further teaches that the first package and the second package are one of a dual die package (DDP), a quadruple die package (QDP), an octuple die package (ODP), a hexadecimal die package (HDP), or a 32 die package (32DP) (Figure 4 shows memory package 50 with two die groups 51 and 52. Each die group shows 3 memory dies and includes an ellipsis, indicating additional dies. Thus, one of ordinary skill would recognize figure 4 implying an octuple die package.).
In regards to claim 19, Ryu teaches a storage device comprising:
a plurality of NAND packages (first to fourth memory packages 50-1 to 50-4 and first to fourth package groups 101 to 104, figure 3; “In this specification, for convenience of description, a case where the memory device 100 is a NAND flash memory is described.”, paragraph 0037);
a controller (memory controller 200, figure 3) configured to control the plurality of NAND packages through a plurality of channels (first to fourth channels CH1 to CH4, figure 3); and
a plurality of chip enable (CE) signal lines configured to transfer a plurality of CE signals respectively corresponding to the plurality of channels of the plurality of NAND packages (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
wherein the plurality of NAND packages include
a first NAND package including a plurality of first dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061) and a first CE pin connected in common to at least one of the plurality of first dies (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046), and
a second NAND package including a plurality of second dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061) and a second CE pin connected in common to at least one of the plurality of second dies (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
the controller includes a third CE pin configured to output a first CE signal corresponding to a first channel among the plurality of channels (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046), and
the plurality of CE signal lines include a first CE signal line including
a first end connected to the third CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046), and
a second end connected in common to the first CE pin and the second CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046).
Ryu fails to teach that each of the first and second NAND packages includes an identification pin applied with a package identification voltage for distinguishing the first NAND package and the second NAND package. Concordel teaches that each of the first and second NAND packages includes an identification pin applied with a package identification voltage for distinguishing the first NAND package and the second NAND package (“For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip). In such embodiments, the chip compares selected bits of each address that it generate (for example, the two most significant bits of each address) with the locally available package identification data, and processes a given part of an input image data strip only if the compared bits match the locally available package identification data.”, Col. 9, lines 51-62) thereby “distinguishing it from other identical chips” (Col. 9, line 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel such that each of the first and second NAND packages includes an identification pin applied with a package identification voltage for distinguishing the first NAND package and the second NAND package thereby “distinguishing it from other identical chips” (id.).
Claims 2, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2023/0238040) in view of Concordel (US 5,359,694) and Takeyama et al. (US 2015/0131397).
In regards to claim 2, Ryu further teaches that the first CE signal line is connected in common to the first CE pin and the second CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel.”, paragraph 0046).
Ryu in view of Concordel fails to teach that the first package includes a first CE pin connected in common to CE pads of the first dies, and
the second package includes a second CE pin connected in common to CE pads of the second dies.
Takeyama teaches that the first package includes a first CE pin connected in common to CE pads of the first dies (“A chip pad 26CE serving as a CE pin of the memory chip #0 of the first stack and a chip pad 26CE serving as a CE pin of the memory chip #1 of the third stack are electrically connected to an identical bonding pad 27CE by the bonding wire 9. This bonding pad 27CE is connected via the wiring patterns of the wiring substrate 7 and the through-hole 23 to the CE pin CE0 of the memory package 15 shown in FIG. 16.”, paragraph 0087), and
the second package includes a second CE pin connected in common to CE pads of the second dies (“A chip pad 26CE serving as a CE pin of the memory chip #0 of the first stack and a chip pad 26CE serving as a CE pin of the memory chip #1 of the third stack are electrically connected to an identical bonding pad 27CE by the bonding wire 9. This bonding pad 27CE is connected via the wiring patterns of the wiring substrate 7 and the through-hole 23 to the CE pin CE0 of the memory package 15 shown in FIG. 16.”, paragraph 0087)
in order to reduce the cost by reducing the number of pins (paragraph 0004).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Takeyama such that the first package includes a first CE pin connected in common to CE pads of the first dies, and
the second package includes a second CE pin connected in common to CE pads of the second dies
in order to reduce the cost by reducing the number of pins (id.).
In regards to claim 17, Ryu further teaches that wherein the first package further includes third dies (“Referring to FIG. 4, the memory package 50 may include a first die group 51, a second die group 52, and an interface 53.”, paragraph 0060),
the second package further includes fourth dies (“Referring to FIG. 4, the memory package 50 may include a first die group 51, a second die group 52, and an interface 53.”, paragraph 0060), and
the first CE signal line and the first command signal line correspond to a first channel (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel.”, paragraph 0046).
Ryu in view of Concordel fails to teach a second CE signal line connected in common to the first and second packages; and
a second command signal line connected in common to the first and second packages,
the controller is configured to select one die of the third dies and fourth dies by applying the CE signal to the second CE signal line and applying the CER command signal to the second command signal line, and
the second CE signal line and the second command signal line correspond to a second channel.
Takeyama teaches a second CE signal line connected in common to the first and second packages (“The memory package 15 includes sixteen memory chips #0 to #15 and eight chip enable pins /CE0 to /CE7. ‘/’ that denotes a negative logic is omitted below. That is, in this package 15, one chip enable pin of the memory package 15 is electrically connected to chip enable pins of two memory chips by an internal wire 5.”, paragraph 0034); and
a second command signal line connected in common to the first and second packages (“The memory chips #0, #1, #4, and #5 are connected to the channel 0 (ch0), the memory chips #2, #3, #6, and #7 are connected to the channel 1 (ch1), the memory chips #8, #9, #12, and #13 are connected to the channel 2 (ch2), and the memory chips #10, #11, #14, and #15 are connected to the channel 3 (ch3).”, paragraph 0035; “The NAND I/F 30 includes control I/O (Ctrl I/O) signals of a plurality of channels (in this case, four channels ch0 to ch3), a plurality of chip enable signals /CE0 to /CEn, and a plurality of ready/busy signals (R/B0 to R/Bm). The Ctrl I/O signals include, as control signal lines, a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (/WE), a read enable signal (/RE), a write protect signal (/WP), a data strobe signal (DQS), and the like, and include, as commands, addresses, and data signal lines, I/O signal lines 100 to 107.”, paragraph 0031),
the controller is configured to select one die of the third dies and fourth dies by applying the CE signal to the second CE signal line and applying the CER command signal to the second command signal line (“Generally, by asserting a CE pin by the chip enable signal CE, one or a plurality of memory chips connected to the asserted CE pin can be selected among a plurality of memory chips in the memory package 15, and one memory chip can be selected among the selected one or plurality of memory chips by the chip address CADD.”, paragraph 0037; “As explained later, several high-order bits (3 bits in the first embodiment) of a combined address are used as the chip address CADD serving as a chip identification bit that identifies a memory chip.”, paragraph 0044), and
the second CE signal line and the second command signal line correspond to a second channel (“The memory chips #0, #1, #4, and #5 are connected to the channel 0 (ch0), the memory chips #2, #3, #6, and #7 are connected to the channel 1 (ch1), the memory chips #8, #9, #12, and #13 are connected to the channel 2 (ch2), and the memory chips #10, #11, #14, and #15 are connected to the channel 3 (ch3).”, paragraph 0035; “The NAND I/F 30 includes control I/O (Ctrl I/O) signals of a plurality of channels (in this case, four channels ch0 to ch3), a plurality of chip enable signals /CE0 to /CEn, and a plurality of ready/busy signals (R/B0 to R/Bm). The Ctrl I/O signals include, as control signal lines, a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (/WE), a read enable signal (/RE), a write protect signal (/WP), a data strobe signal (DQS), and the like, and include, as commands, addresses, and data signal lines, I/O signal lines 100 to 107.”, paragraph 0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Takeyama to include a second CE signal line connected in common to the first and second packages; and
a second command signal line connected in common to the first and second packages,
the controller is configured to select one die of the third dies and fourth dies by applying the CE signal to the second CE signal line and applying the CER command signal to the second command signal line, and
the second CE signal line and the second command signal line correspond to a second channel
in order to increase memory bandwidth.
In regards to claim 20, Ryu teaches a storage device comprising:
a first package (first memory package 50-1, figure 3) including
a first chip enable (CE) pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
first dies (“The first die group 51 may include a plurality of memory dies.”, paragraph 0061) connected in common to the first CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046), and
second dies (second die group 52, figure 5);
a second package (second memory package 50-2, figure 3) including
a third CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
third dies connected in common to the third CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046), and
fourth dies (second die group 52, figure 5);
a controller (memory controller 200, figure 3) including
a fifth CE pin configured to output a first CE signal corresponding to a first channel (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel.”, paragraph 0046), and
a sixth CE pin configured to output a second CE signal corresponding to a second channel (id.; first to fourth channels CH1 to CH4, figure 3);
a first CE signal line (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel.”, paragraph 0046) including
a first end connected to the fifth CE pin (id.), and
a second end connected in common to the first CE pin and the third CE pin (id.); and
a second CE signal line (id.; first to fourth channels CH1 to CH4, figure 3) including
a first end connected to the sixth CE pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel.”, paragraph 0046), and
a second end connected in common to a second CE pin and a fourth CE pin (id.).
Ryu fails to teach the first package including
the second CE pin, and
second dies connected in common to the second CE pin;
the second package including
the fourth CE pin, and
fourth dies connected in common to the fourth CE pin;
wherein each of the first and second packages includes an identification pin applied with an identification voltage for distinguishing the first and second packages.
Concordel teaches that each of the first and second packages includes an identification pin applied with an identification voltage for distinguishing the first and second packages (“For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip). In such embodiments, the chip compares selected bits of each address that it generate (for example, the two most significant bits of each address) with the locally available package identification data, and processes a given part of an input image data strip only if the compared bits match the locally available package identification data.”, Col. 9, lines 51-62) thereby “distinguishing it from other identical chips” (Col. 9, line 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel such that each of the first and second packages includes an identification pin applied with an identification voltage for distinguishing the first and second packages thereby “distinguishing it from other identical chips” (id.).
Ryu in view of Concordel fails to teach that the first package including
the second CE pin, and
second dies connected in common to the second CE pin; and
the second package including
the fourth CE pin, and
fourth dies connected in common to the fourth CE pin.
Takeyama teaches that the first package including
the second CE pin, and
second dies connected in common to the second CE pin (“The memory package 15 includes sixteen memory chips #0 to #15 and eight chip enable pins /CE0 to /CE7. ‘/’ that denotes a negative logic is omitted below. That is, in this package 15, one chip enable pin of the memory package 15 is electrically connected to chip enable pins of two memory chips by an internal wire 5.”, paragraph 0034); and
the second package including
the fourth CE pin, and
fourth dies connected in common to the fourth CE pin (id.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Takeyama such that the first package including
the second CE pin, and
second dies connected in common to the second CE pin; and
the second package including
the fourth CE pin, and
fourth dies connected in common to the fourth CE pin
in order to increase memory bandwidth.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2023/0238040) in view of Concordel (US 5,359,694) and Oh et al. (US 9,818,707).
In regards to claim 3, Ryu further teaches that the first package includes a first command pin (“For example, the data (DQ) line, the chip enable (CE) line, the write enable (WE) line, the read enable (RE) line, the address latch enable (ALE) line, the command latch enable (CLE) line, the write protect (WP) line, and the ready/busy (RB) line may be included in one channel, and the memory controller 200 and a plurality of memory devices (e.g., a plurality of memory dies) may be connected to each other through the corresponding channel. Therefore, when the memory controller 200 transmits signals through lines included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 among the memory devices connected to the corresponding channel may receive the signals.”, paragraph 0046),
the second package includes a second command pin (id.), and
the first command signal line is connected in common to the first command pin and the second command pin (id.).
Ryu in view of Concordel fails to teach the first command pin connected in common to command pads of the first dies, and
the second command pin connected in common to command pads of the second dies.
Oh teaches the first command pin connected in common to command pads of the first dies (“The chip command-address pad unit 30 may include the r pads for receiving a chip selection signal, a clock enable signal, a row access strobe (RAS) signal, a column access strobe (CAS) signal, a write enable signal, address signals, etc.”, Col. 7, lines 19-23; “The first semiconductor die 200 may be electrically connected to the chip command-address pad unit 30”, Col. 7, lines 29-30; “The second semiconductor die 300 may be electrically connected to the chip command-address pad unit 30”, Col. 7, lines 32-34), and
the second command pin connected in common to command pads of the second dies (“The chip command-address pad unit 30 may include the r pads for receiving a chip selection signal, a clock enable signal, a row access strobe (RAS) signal, a column access strobe (CAS) signal, a write enable signal, address signals, etc.”, Col. 7, lines 19-23; “The first semiconductor die 200 may be electrically connected to the chip command-address pad unit 30”, Col. 7, lines 29-30; “The second semiconductor die 300 may be electrically connected to the chip command-address pad unit 30”, Col. 7, lines 32-34)
“for exchanging signals with an external device” (Col. 1, lines 28-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Oh such that the first command pin connected in common to command pads of the first dies, and
the second command pin connected in common to command pads of the second dies
“for exchanging signals with an external device” (id.).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2023/0238040) in view of Concordel (US 5,359,694) and Park (US 2022/0189914).
In regards to claim 6, Ryu in view of Concordel teaches claim 1. Ryu in view of Concordel fails to teach that each of the first dies and the second dies includes at least one die identification pad applied with at least one die identification voltage respectively corresponding to the at least one die identification bit. Park teaches that each of the first dies and the second dies includes at least one die identification pad (“Particularly, some of the plurality of chip pads CP may function as chip identification pads CP1, CP2, and CP3 for respectively identifying the first to eighth semiconductor chips 111 to 118 included in the chip stack 110.”, paragraph 0032) applied with at least one die identification voltage respectively corresponding to the at least one die identification bit (“Referring to FIGS. 1B and 1C, each of the first to third chip identification pads CP1, CP2, and CP3 in the first to eighth semiconductor chips 111 to 118 may be in a state in which the power is applied or in a floating state. Here, the applied power may include various levels of voltages. For example, the applied power may be a power supply voltage (VDD). The state in which the power is applied to any one of the first to third chip identification pads CP1, CP2, and CP3 may be represented by a logical value ‘1’, and the floating state may be represented by a logical value ‘0’.”, paragraph 0037) in order that the chips may be distinguished from each other (paragraph 0036). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Park such that each of the first dies and the second dies includes at least one die identification pad applied with at least one die identification voltage respectively corresponding to the at least one die identification bit in order that the chips may be distinguished from each other (id.).
In regards to claim 7, Concordel further teaches that each of the first dies and the second dies is respectively connected to the at least one identification pin (“For example, the package identification data can be provided by asserting appropriate voltage levels to a set of pins protruding from the chip, or by storing the package identification data in an internal memory within the chip (such as by programming a PROM within the chip). In such embodiments, the chip compares selected bits of each address that it generate (for example, the two most significant bits of each address) with the locally available package identification data, and processes a given part of an input image data strip only if the compared bits match the locally available package identification data.”, Col. 9, lines 51-62). Park further teaches that each of the first dies and the second dies includes at least one additional identification pad (“Some of the plurality of chip pads CP may function as stack identification pads CPO for distinguishing the second chip stack 220 from the first chip stack 210, and chip identification pads CP1 and CP2 for identifying the first to fourth semiconductor chips 221 to 224 included in the second chip stack 220.”, paragraph 0055).
In regards to claim 8, Concordel further teaches that the selected one die includes
a package identification pad applied with a package identification voltage corresponding to a bit value of a package identification bit included in the CER command signal (“In such embodiments, the chip compares selected bits of each address that it generate (for example, the two most significant bits of each address) with the locally available package identification data, and processes a given part of an input image data strip only if the compared bits match the locally available package identification data.”, Col. 9, lines 56-62).
Park further teaches that the selected one die includes a die identification pad applied with a die identification voltage (“Referring to FIGS. 1B and 1C, each of the first to third chip identification pads CP1, CP2, and CP3 in the first to eighth semiconductor chips 111 to 118 may be in a state in which the power is applied or in a floating state. Here, the applied power may include various levels of voltages. For example, the applied power may be a power supply voltage (VDD). The state in which the power is applied to any one of the first to third chip identification pads CP1, CP2, and CP3 may be represented by a logical value ‘1’, and the floating state may be represented by a logical value ‘0’.”, paragraph 0037).
Ryu further teaches that the selected one die includes the die identification corresponding to a bit value of a die identification bit included in the CER command signal (“In accordance with an embodiment of the present disclosure, the storage device 1000 may address the memory die by further using a data (DQ) signal input during the predetermined N cycles, where N is a natural number.”, paragraph 0125).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2023/0238040) in view of Concordel (US 5,359,694) and Keeth et al. (US 2020/0272560).
In regards to claim 9, Ryu in view of Concordel teaches claim 1. Ryu in view of Concordel fails to teach that the first package includes a first buffer configured to receive the CER command signal and to transfer the received CER command signal to the first dies in response to the CE signal, and
the second package includes a second buffer configured to receive the CER command signal and to transfer the received CER command signal to the second dies in response to the CE signal.
Keeth teaches that the first package includes a first buffer (“The memory devices 120A, 120B, each include a buffer assembly, here in the example form of a buffer die 128, coupled to a secondary substrate 124. Although the terminology ‘buffer die’ is used herein for referencing the buffer assembly, any such ‘buffer die’ described herein may be in the form of an assembly including, for example, one or more semiconductor die or other devices and/or other discrete components (whether or not packaged together) providing the described functionality.”, paragraph 0039) configured to receive the CER command signal (“Communication from the buffer die 300 to a host device is indicated by arrows 322 and 324. In FIG. 3, arrows 324 denote communication from command/address (CA) pins, and arrows 322 denote communication from data (DQ) pins 322.”, paragraph 0045) and to transfer the received CER command signal to the first dies in response to the CE signal (“In one example, a given command/address path on the DRAM interface 314 side of the buffer die 300 is in communication with multiple DRAM dies.”, paragraph 0053), and
the second package includes a second buffer (“The memory devices 120A, 120B, each include a buffer assembly, here in the example form of a buffer die 128, coupled to a secondary substrate 124. Although the terminology ‘buffer die’ is used herein for referencing the buffer assembly, any such ‘buffer die’ described herein may be in the form of an assembly including, for example, one or more semiconductor die or other devices and/or other discrete components (whether or not packaged together) providing the described functionality.”, paragraph 0039) configured to receive the CER command signal (“Communication from the buffer die 300 to a host device is indicated by arrows 322 and 324. In FIG. 3, arrows 324 denote communication from command/address (CA) pins, and arrows 322 denote communication from data (DQ) pins 322.”, paragraph 0045) and to transfer the received CER command signal to the second dies in response to the CE signal (“In one example, a given command/address path on the DRAM interface 314 side of the buffer die 300 is in communication with multiple DRAM dies.”, paragraph 0053)
“to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side” (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Keeth such that the first package includes a first buffer configured to receive the CER command signal and to transfer the received CER command signal to the first dies in response to the CE signal, and
the second package includes a second buffer configured to receive the CER command signal and to transfer the received CER command signal to the second dies in response to the CE signal
“to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side” (id.).
In regards to claim 11, Ryu in view of Concordel teaches claim 1. Ryu in view of Concordel fails to teach that the first package includes a third buffer configured to
receive the CE signal and the CER command signal, and
to transfer the received CE signal and the received CER command signal to the first dies, and
the second package includes a fourth buffer configured to
receive the CE signal and the CER command signal, and
to transfer the received CE signal and the received CER command signal to the second die.
Keeth teaches that the first package includes a third buffer (“The memory devices 120A, 120B, each include a buffer assembly, here in the example form of a buffer die 128, coupled to a secondary substrate 124. Although the terminology ‘buffer die’ is used herein for referencing the buffer assembly, any such ‘buffer die’ described herein may be in the form of an assembly including, for example, one or more semiconductor die or other devices and/or other discrete components (whether or not packaged together) providing the described functionality.”, paragraph 0039) configured to
receive the CE signal and the CER command signal (“Communication from the buffer die 300 to a host device is indicated by arrows 322 and 324. In FIG. 3, arrows 324 denote communication from command/address (CA) pins, and arrows 322 denote communication from data (DQ) pins 322.”, paragraph 0045), and
to transfer the received CE signal and the received CER command signal to the first dies (“In one example, a given command/address path on the DRAM interface 314 side of the buffer die 300 is in communication with multiple DRAM dies.”, paragraph 0053), and
the second package includes a fourth buffer (“The memory devices 120A, 120B, each include a buffer assembly, here in the example form of a buffer die 128, coupled to a secondary substrate 124. Although the terminology ‘buffer die’ is used herein for referencing the buffer assembly, any such ‘buffer die’ described herein may be in the form of an assembly including, for example, one or more semiconductor die or other devices and/or other discrete components (whether or not packaged together) providing the described functionality.”, paragraph 0039) configured to
receive the CE signal and the CER command signal (“Communication from the buffer die 300 to a host device is indicated by arrows 322 and 324. In FIG. 3, arrows 324 denote communication from command/address (CA) pins, and arrows 322 denote communication from data (DQ) pins 322.”, paragraph 0045), and
to transfer the received CE signal and the received CER command signal to the second die (“In one example, a given command/address path on the DRAM interface 314 side of the buffer die 300 is in communication with multiple DRAM dies.”, paragraph 0053)
“to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side” (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ryu with Concordel and Keeth such that the first package includes a third buffer configured to
receive the CE signal and the CER command signal, and
to transfer the received CE signal and the received CER command signal to the first dies, and
the second package includes a fourth buffer configured to
receive the CE signal and the CER command signal, and
to transfer the received CE signal and the received CER command signal to the second die
“to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side” (id.).
Allowable Subject Matter
Claims 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach that a buffer includes a package identification pad in conjunction with the other claim limitations, nor would it have been obvious.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Eilert (US 2005/0010725) teaches device IDs for stacked devices. Yang (US 11,080,218) teaches a chip enable reduction command. Kim (US 2022/0157353) teaches a memory package with a buffer chip. Kang (US 2022/0236917) teaches a chip enable for daisy chained chips. Hiyamizu (US 2022/0301635) teaches setting LUNs from signal bonding pads. Park (US 12,493,548) teaches memory chips sharing control signal lines. Yu (US 2025/0378884) teaches MDS pads to indicate an identifier. Son (US 2026/0127110) teaches identifiers for each chip.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 29 June 2026
Prosecution Insights