DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
In light of the amendment filed 6/8/26, the objection to claim 5 for informalities is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tomitani (US 2019/0164485) in view of Ka et al. (US 2019/0130835).
Regarding claim 1, Tomitani discloses a display device comprising: a display panel including a plurality of pixels (abstract, figs. 2-3, ¶ 35-40);
a data driver configured to apply a data voltage to the display panel (figs. 2-3, ¶ 40-43, drive circuit 54);
a gate driver configured to output a gate signal to the pixels (figs. 2-3, ¶ 40-43, drive circuit 52);
and a voltage generator configured to apply a low power voltage and an initialization voltage to the display panel (figs. 2-3, ¶ 40-47, e.g., circuits 58, 81),
wherein the display panel includes a first display region and a reference display region (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients),
wherein at least one pixel of the pixels includes: a driving transistor configured to generate a driving current based on the data voltage (fig. 3, ¶ 49-57, drive transistor 92);
a light emitting element including a first electrode configured to receive the driving current and a second electrode configured to receive the low power voltage (fig. 3, ¶ 49-57, OLED 90);
and an initialization transistor (fig. 3, ¶ 49-57, e.g., switch 96, see ¶ 63-64; see also fig. 12),
wherein the initialization voltage includes a first region initialization voltage and a reference region initialization voltage (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99),
and wherein the first region initialization voltage applied to the first display region is different from the reference region initialization voltage applied to the reference display region (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99),
and wherein the first region initialization voltage is determined based on luminance uniformity between the first display region and the reference display region (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients).
Tomitani fails to explicitly disclose an initialization transistor configured to apply the initialization voltage to the first electrode of the light emitting element.
Ka teaches an initialization transistor configured to apply the initialization voltage to the first electrode of the light emitting element (fig. 2, ¶ 74, M7; see also figs. 11-14).
Tomitani and Ka are both directed to pixel initialization for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Tomitani with the device of Ka since such a modification allows a quantity of charges accumulated in the OLED to be initialized (Ka, ¶ 74) and prevents color dragging (Ka, ¶ 157).
Regarding claim 2, Tomitani discloses wherein the first region initialization voltage is generated based on a reference initialization voltage and an initialization offset voltage (figs. 6-10, ¶ 82-87; see also ¶ 92-99, e.g., ¶ 93, initialization signals calculated by adding correction coefficient values to initial potential Vinf),
and wherein the initialization offset voltage is calculated based on a difference of a luminance uniformity between the reference display region and the first display region (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients).
Regarding claim 3, Tomitani discloses wherein the difference of the luminance uniformity is determined by changing the first region initialization voltage (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99, initialization potentials supplied to achieve substantially uniform luminance in X and Y directions),
and wherein the initialization offset voltage is calculated based on a changed first region initialization voltage in a minimum luminance uniformity in which the difference of the luminance uniformity is minimum (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99, initialization potentials supplied to achieve substantially uniform luminance in X and Y directions).
Regarding claim 4, Tomitani discloses wherein the luminance uniformity is a ratio between a luminance for which a reference data voltage is applied to the reference display region and a luminance for which the reference data voltage is applied to the first display region (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region], see fig. 7, VINI proportional to distance from power source; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients).
Regarding claim 5, Tomitani discloses wherein based on the reference data voltage being applied to the reference display region, the reference display region is configured to emit as a target luminance (figs. 6-10, ¶ 82-87; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients).
Regarding claim 9, Tomitani discloses wherein the display panel further includes a second display region (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region]; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients),
wherein the initialization voltage further includes a second region initialization voltage, and wherein the second region initialization voltage applied to the second display region is inconsistent with the first region initialization voltage and the reference region initialization voltage (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region], see fig. 7, VINI proportional to distance from power source; see also ¶ 92-99, monochrome raster displayed to determine luminance non-uniformity between regions and calculate correction coefficients).
Regarding claim 10, Tomitani discloses wherein the first region initialization voltage is higher than the reference region initialization voltage (figs. 6-10, ¶ 82-87, luminance non-uniformity corrected in X and Y direction, e.g., initialization voltage relatively high at columns at opposite ends of each horizontal scan period [reference region(s)] relative to center region [first region], see fig. 7, VINI proportional to distance from power source; see also ¶ 92-99).
Regarding claim 11, Ka further teaches an emission driver configured to output an emission signal to the at least one pixel (figs. 1-2, ¶ 63, driver 30),
wherein the at least one pixel of the pixels includes: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node (figs. 1-2, ¶ 69-75, M1);
a second transistor configured to apply the data voltage to the second node in response to a write gate signal (figs. 1-2, ¶ 69-75, M2);
a third transistor configured to connect the first node and the third node in response to a compensation gate signal (figs. 1-2, ¶ 69-75, M3);
a fourth transistor configured to apply a data initialization voltage to the first node in response to an initialization gate signal (figs. 1-2, ¶ 69-75, M4);
a fifth transistor configured to apply a high power voltage to the second node in response to the emission signal (figs. 1-2, ¶ 69-75, M5);
a sixth transistor configured to connect the third node and a fourth node in response to the emission signal (figs. 1-2, ¶ 69-75, M6);
and a seventh transistor configured to apply the initialization voltage to the fourth node in response to the write gate signal (figs. 1-2, ¶ 69-75, M7),
wherein the first transistor is the driving transistor, and the seventh transistor is the initialization transistor (figs. 1-2, ¶ 69-75),
and wherein the first electrode of the light emitting element is connected to the fourth node (figs. 1-2, ¶ 69-75, OLED1).
Regarding claim 12, this claim is rejected under the same rationale as claim 1.
Regarding claim 13, this claim is rejected under the same rationale as claim 2.
Regarding claim 14, this claim is rejected under the same rationale as claim 3.
Regarding claim 15, this claim is rejected under the same rationale as claim 4.
Regarding claim 18, this claim is rejected under the same rationale as claim 10.
Regarding claim 19, Tomitani discloses an electronic device comprising: a display panel including a plurality of pixels (abstract, figs. 2-3, ¶ 35-40);
a display panel driver configured to drive the display panel based on input image data and an input control signal (figs. 1-3, ¶ 35-43, e.g., drive circuit 40);
a processor configured to output the input image data and the input control signal (figs. 1-3, ¶ 35-43, e.g., signal processing circuit);
and a power manager configured to output a driving voltage to the display panel (figs. 2-3, ¶ 35-47, e.g., power supply circuit).
The remaining limitations of claim 19 are rejected under the same rationale as claim 1.
Regarding claim 20, this claim is rejected under the same rationale as claim 2.
Claims 6-8 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tomitani in view of Ka as applied to claims 2 and 13 above, and further in view of Sakikawa et al. (US 2020/0006712).
Regarding claim 6, Tomitani in view of Ka fails to explicitly disclose wherein the display panel is generated based on a mother panel, and wherein the reference initialization voltage is generated based on a location data of the display panel in the mother panel.
Sakikawa teaches wherein the display panel is generated based on a mother panel, and wherein the reference initialization voltage is generated based on a location data of the display panel in the mother panel (abstract, figs. 1-2, ¶ 41-45, distribution data of necessary light emission voltage on the mother substrate calculated to correct for luminance unevenness between display panels 8; see also ¶ 54-61).
Tomitani in view of Ka and Sakikawa are both directed to luminance correction for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Tomitani in view of Ka with the mother substrate correction of Sakikawa since such a modification provides the inspection process can be shortened while luminance unevenness between display panels is reduced (Sakikawa, ¶ 18).
Regarding claim 7, Sakikawa further teaches wherein the mother panel includes a first mother region and a second mother region (figs. 1-2, ¶ 41-45, distribution data of necessary light emission voltage on the mother substrate calculated to correct for luminance unevenness between display panels 8; matrix of panels 8 disclosed; see also ¶ 54-61),
and wherein a reference initialization voltage of a display panel generated from the first mother region is higher than a reference initialization voltage of a display panel generated from the second mother region (figs. 1-2, ¶ 41-45, distribution data of necessary light emission voltage on the mother substrate calculated to correct for luminance unevenness between display panels 8; matrix of panels 8 disclosed, e.g., central rows/columns and edge rows/columns disclosed; see also ¶ 54-61).
Regarding claim 8, Sakikawa further teaches wherein the mother panel includes a center region and an edge region, and wherein the first mother region is the edge region and a second mother region is the center region (figs. 1-2, ¶ 41-45, distribution data of necessary light emission voltage on the mother substrate calculated to correct for luminance unevenness between display panels 8; matrix of panels 8 disclosed, e.g., central rows/columns and edge rows/columns disclosed; see also ¶ 54-61).
Regarding claim 16, this claim is rejected under the same rationale as claim 6.
Regarding claim 17, this claim is rejected under the same rationale as claim 7.
Response to Arguments
Applicant's arguments filed 6/8/26 have been fully considered but they are not persuasive. Regarding claims 1, 12, and 19, Applicant argues Tomitani does not disclose or suggest “determining luminance uniformity between a first display region and a reference display region” but rather “appears to merely disclose generalized positional compensation techniques applied across a display panel” (Remarks, pp. 11-12).
Examiner disagrees. As cited above, ¶ 92 of Tomitani explicitly discloses a monochrome raster is displayed to determine luminance non-uniformity between regions and calculate correction coefficients for correcting initialization voltage signals. Further, ¶ 97 of Tomitani explicitly states that the initialization potentials to be supplied to respective pixels are generated to achieve “uniform luminance” in both the X and Y directions.
The rejection of the claims is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
