DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 11, 13 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. 20160110250 herein Han in view of Park 20190108136 herein Park.
Per claim 1, Han discloses: a data buffer configured to store data to be received from or transmitted to a host; (fig. 3, L1 cache, ¶0072; the processor write buffer 3215 is a buffer for storing write data received from the processor 3300 and the corresponding address. The processor 3300 may check a write data error stored in the processor write buffer 3215. When there is no error, the processor 3300 may provide a write data fault-free signal to the processor error checking unit 3216) … search engine configured to store a plurality of entries access-requested by the host; (¶0073; the processor error checking unit 3216 may control to write the address and the data stored in the processor write buffer 3215 in the tag memory 3211 and the data memory 3212, respectively, and set each dirty bit of the tag memory 3211 and the data memory 3212 to be ‘1’. It may thus reduce errors of the L1 cache by determining whether there is a data error or not before the data is reflected to the L1 cache 3210) and a device controller configured to provide the host with a read fail response when it is determined that a read operation on data stored in a memory block fails, and to search for recovery data to substitute the data stored at a read fail address of the memory block from at least one of the data buffer and the … search engine in response to a recovery data search command received from the host (fig. 2, ¶0058-60; when data is requested from a processor to a L1 cache, any data error and/or tag error of the L1 cache is checked.. When it is determined as that any data error and/or tag error is in the L1 cache, it is determined whether the error in the L1 cache is recoverable by using a dirty bit value of the L1 cache. According to the result, the first type error signal representing that a recoverable error is occurred in the L1 cache or the second type error signal representing that an unrecoverable error is occurred in the L1 cache is generated in S220… In an embodiment, when all L1dirty bit values are ‘0’, the error is recoverable in the L1 cache so that the first type error signal is generated. A L2 cache read request signal may be also generated to recover the error).
Han discloses searching and recovering the data but does not specifically disclose: a linear search engine.
However, Park does disclose: a linear search engine (¶0020; generating a logical address list, in which values of logical addresses of the commands stored in the command queue are arranged in order; and determining whether the logical address of the piece of selected mapping information corresponds to any one among the values in the logical address list through a binary search scheme or a linear search scheme).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Han and Park’s cache and search scheme to determine what is maintained in the cache. Park improves efficiency of mapping information (¶0005).
Per claim 4, Han discloses: wherein the device controller searches for, as the recovery data, data corresponding to the read fail address in the data buffer ((fig. 2, ¶0058-60; when data is requested from a processor to a L1 cache, any data error and/or tag error of the L1 cache is checked.. When it is determined as that any data error and/or tag error is in the L1 cache, it is determined whether the error in the L1 cache is recoverable by using a dirty bit value of the L1 cache. According to the result, the first type error signal representing that a recoverable error is occurred in the L1 cache or the second type error signal representing that an unrecoverable error is occurred in the L1 cache is generated in S220…).
Per claim 5, Han discloses: wherein the device controller searches for the recovery data through the linear search engine when the recovery data is not detected in the data buffer (fig. 3, L1 cache, ¶0072; The processor 3300 may check a write data error stored in the processor write buffer 3215. When there is no error, the processor 3300 may provide a write data fault-free signal to the processor error checking unit 3216; ¶0073; the processor error checking unit 3216 may control to write the address and the data stored in the processor write buffer 3215 in the tag memory 3211 and the data memory 3212, respectively, and set each dirty bit of the tag memory 3211 and the data memory 3212 to be ‘1’.).
Claims 11 and 13 are the method claims corresponding to the device claims 1, 4 and 5 and is rejected under the same reasons set forth in connection with the rejection of claims 1, 4 and 5.
Claim 17 is the system claim corresponding to the device claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim 20 is the system claim corresponding to the device claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim(s) 2-3, 12, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. 20160110250 herein Han and Park 20190108136 herein Park in view of Tkacik et al. 20220350503 herein Tkacik.
Per claim 2, the combined teaching of Han and Park disclose searching recovery data but does not specifically disclose: wherein the device controller receives the recovery data search command from the host after entering an idle state, based on whether a priority order of the read operation is urgent.
However, Tkacik discloses: wherein the device controller receives the recovery data search command from the host after entering an idle state, based on whether a priority order of the read operation is urgent (¶0043; Memory scrubbing of memory is done to correct for errors that may occur in memory due to, for example, radiation. Memory scrubbing is performed as a background task that is it carried out when there is idle time or as a low priority task. The memory scrubber 230 may simply cycle through the memory in a sequential order.; the examiner interprets the limitation if priority is low the recovery is done while idle).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Han, Park and Tkacik’s low bandwidth memory scrubber to correct bit errors for each memory location. Tkacik memory scrubber improves memory performance (¶0034; Memory scrubbing is a low bandwidth background process, so that the key refresh occurs, but imperceptibly to the users of system memory and without affecting the performance of the memory. Also, the memory may continue to be used during the scrubbing process).
Per claim 3, Tkacik discloses: wherein the device controller, in response to a rewrite command received from the host, writes the recovery data and remaining data except the data stored at the read fail address in the memory block to another memory block, and processes the memory block as a bad block (¶0043; Memory scrubbing of memory is done to correct for errors that may occur in memory due to, for example, radiation. Memory scrubbing is performed as a background task that is it carried out when there is idle time or as a low priority task. The memory scrubber 230 may simply cycle through the memory in a sequential order. When a memory location is to be refreshed, the memory scrubber 230 sends a refresh request to the address/command logic 232. The address/command logic sends a read request to the DRAM for the location to be scrubbed. Then the data read from the DRAM is checked, and if an error is found the data corrected. The corrected data and ECC is then written back to the DRAM fig. 2,; the examiner interprets the limitation as recovering the data in case of the read fail).
Claim 12 is the method claim corresponding to the device claim 2 and is rejected under the same reasons set forth in connection with the rejection of claims 2.
Claim 16 is the method claim corresponding to the device claim 3 and is rejected under the same reasons set forth in connection with the rejection of claims 3.
Claim 18 is the system claim corresponding to the device claims 2-3 and is rejected under the same reasons set forth in connection with the rejection of claims 2-3.
Claim(s) 6-8, 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. 20160110250 herein Han and Park 20190108136 herein Park in view of Hyun et al. 20160170871 herein Hyun.
Per claim 6, the combined teachings of Han and Park do not specifically disclose: wherein each of the plurality of entries includes a start address of a sequential address access-requested by the host, a length of the sequential address, and data patterns extracted from data stored at the sequential address.
However, Hyun discloses: wherein each of the plurality of entries includes a start address of a sequential address access-requested by the host, a length of the sequential address, and data patterns extracted from data stored at the sequential address (¶0050; The persistent contextual metadata may include, but is not limited to: a logical address of the data, an identifier of the data (e.g., a file name, object id, label, unique identifier, or the like), reference(s) to other data (e.g., an indicator that the data is associated with other data), a relative position or offset of the data with respect to other data (e.g., file offset, etc.), data size and/or range, and the like. The contextual data format may comprise a packet format comprising a data segment and one or more headers.; the examiner notes that the data pattern interpreted as encoded/coded/ecc data used to recreate data).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Han, Park and Hyun parameter configuration of write or programming of a non-volatile memory to reduce storage and processing overhead. (¶0037; the configuration module 150 may store fewer configuration parameters, may efficiently determine values for configuration parameters using a model instead of determining each value by reading the media 122, or the like, resulting in a reduction in configuration parameter storage overhead and/or processing overhead, when compared to other systems and devices which may determine and/or store configuration parameters individually).
Per claim 7, Park discloses: wherein the device controller detects a target entry including the read fail address among the plurality of entries in the linear search engine, and detects, as the recovery data, data generated using data patterns corresponding to the target entry (¶0207; The ECC circuit 6322 may calculate an ECC value of data to be programmed to the memory device 6340 during a program operation. The ECC circuit 6322 may perform an error correction operation on data read from the memory device 6340 based on the ECC value during a read operation. The ECC circuit 6322 may perform an error correction operation on data recovered from the memory device 6340 during a failed data recovery operation).
Per claim 8, Hyun discloses: wherein the recovery data includes at least one of data inferred based on data with a history of being stored at the read fail address, and data with a history of being stored at a logical block address sequential to the read fail address (¶0169; the adjustment module 406 may select an amount to adjust the read voltage threshold based on one or more factors such as age, amount of wear, usage history, error history, or other aspects of the non-volatile memory media 122.).
Claim 14-15 is the method claims corresponding to the device claims 6-7 and are rejected under the same reasons set forth in connection with the rejection of claims 6-7.
Claim 19 is the system claims corresponding to the device claim 8 and is rejected under the same reasons set forth in connection with the rejection of claim 8.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. 20160110250 herein Han and Park 20190108136 herein Park in view of Ilic et al. 20210182188 herein Ilic.
Per claim 9, the combined teachings of Han and Park do not specifically disclose: wherein each of the plurality of entries includes a start address of a sequential address access-requested by the host, a length of the sequential address, and data patterns extracted from data stored at the sequential address.
However, Ilic discloses: wherein the storage device further comprises a logical block address history table including physical block addresses with a history of being mapped to the read fail address, and wherein the device controller detects, as the recovery data, data stored at a physical block address previously mapped to the read fail address as compared with a physical block address currently mapped to the read fail address in the logical block address history table (¶0056; If the model can predict earlier that the block will be marked as bad, firmware can schedule the block for relocation and recycling earlier. Therefore, proactive block retirement can be completed sooner. In addition, if there a is random read coming from a host, there will also be less and/or no delay caused due to the relocation and recycling of the grown defect, thereby improving random read performance; ¶0058; Table 504 stores various block-level information about the blocks that have gone bad such as the RAID block to which a given block belongs, a LUN assigned to the block, a channel identifier, a plane identifier, the origin of the problem that caused the block to go bad (e.g. grown or at manufacturing), whether the defect occurred due to erase or program operations, program/erase cycles per RAID block, and a partition identity).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Han, Park and Ilic’s time series data indicative of a history of bad blocks to avoid bad blocks in future writes. Illic’s proactive block retirement improves read performance. (¶0056; If the model can predict earlier that the block will be marked as bad, firmware can schedule the block for relocation and recycling earlier. Therefore, proactive block retirement can be completed sooner. In addition, if there a is random read coming from a host, there will also be less and/or no delay caused due to the relocation and recycling of the grown defect, thereby improving random read performance).
Per claim 10, Hyun discloses: wherein the storage device further includes a logical-to-physical mapping table including mapping information between a logical block address and a physical block address, and wherein the device controller detects, as the recovery data, data predicted based on data stored at sequential addresses in a predetermined range, which include the read fail address, in the logical-to-physical mapping table (¶0056; If the model can predict earlier that the block will be marked as bad, firmware can schedule the block for relocation and recycling earlier. Therefore, proactive block retirement can be completed sooner. In addition, if there a is random read coming from a host, there will also be less and/or no delay caused due to the relocation and recycling of the grown defect, thereby improving random read performance; ¶0058; Table 504 stores various block-level information about the blocks that have gone bad such as the RAID block to which a given block belongs, a LUN assigned to the block, a channel identifier, a plane identifier, the origin of the problem that caused the block to go bad (e.g. grown or at manufacturing), whether the defect occurred due to erase or program operations, program/erase cycles per RAID block, and a partition identity.).
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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