DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a provisional application 63/656,003 filed on 06/04/2024 is acknowledged.
Allowable Subject Matter
Claim 7-9, 18 -20, 25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
For claim 7, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 7 depends.
For claim 8, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 8 depends.
For claim 9, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 9 depends.
For claim 18, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 18 depends.
For claim 19, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 19 depends.
For claim 20, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 20 depends.
For claim 25, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 25 depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 10-16, 21-23 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Talwar (US 20180004456)
Regarding Claim 1, Talwar teaches
A memory system, comprising: one or more memory devices; (Talwar [0011] prioritization of access to a memory shared by multiple devices, systems, compute nodes, applications, or other processing units. [0017] Memory address based prioritization of access to the shared memory)
and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to receive a plurality of commands comprising first commands associated with a first memory space of the memory system that is assigned a first priority of a plurality of priorities, second commands associated with a second memory space of the memory system that is assigned a second priority of the plurality of priorities, and third commands associated with a third memory space of the memory system that is assigned a third priority of the plurality of priorities; (Talwar [0012] FIG. 1, a memory network 100 that supports prioritizing access to a shared memory. [0015] The memory network 100 may govern access to the shared memory by multiple compute nodes. In that regard, the memory network 100 may route memory access requests received from multiple compute nodes to a corresponding portion of the shared memory. [0024] the memory network 100 labels memory access traffic according to memory address range. Memory accesses targeting data with a particular memory address range (or ranges) in the shared memory 201 may be associated with a particular priority level…accesses to a first memory address range in the shared memory 201 may be assigned an elevated (e.g., high) priority level whereas accesses to a second memory address range in the shared memory 201 may be assigned a non-elevated or lower (e.g., normal) priority level.) (i.e., memory address ranges with different priority level are memory spaces assigned different priorities, memory access requests/commands associated with different memory spaces are assigned different priorities)
and execute, in accordance with receiving the plurality of commands, the plurality of command using an interleaving pattern that is in accordance with the first priority, the second priority, and the third priority. (Talwar [0030] Upon determining a priority level for the memory access request 301, the memory network 100 may process the memory access request 301 according to the determined priority level. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme) (i.e., utilize a weighted round robin scheme is using an interleaving pattern)
Regarding Claim 2, Talwar teaches
store, in accordance with receiving the plurality of commands, the plurality of commands into a queue, (Talwar [0030] The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301.)
wherein an order of the plurality of commands in the queue is using the interleaving pattern, (Talwar [0030] In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may utilize a weighted round robin scheme, weighted fair queuing scheme, or any bandwidth share scheme to dequeue access requests from the queues 320 to process)
and wherein the plurality of commands are executed using the order of the plurality of commands in the queue. (Talwar [0030] dequeuing memory access requests from the queues 320 for processing)
Regarding Claim 3, Talwar teaches
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: store, prior to storing the plurality of commands into the queue, the plurality of commands into a second queue using an order the plurality of commands is received, the order the plurality of commands is received being different than the order of the plurality of commands in the queue. (Talwar [0030] the memory network 100 may include multiple queues 320, which may differ according to priority. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301.) (i.e., memory access requests stored in queues based on priority, and the order of commands received is different than the order of commands in the queue)
Regarding Claim 4, Talwar teaches
receive, in accordance with receiving the plurality of commands, fourth commands of the plurality of commands associated with a fourth memory space that is assigned a fourth priority of the plurality of priorities and is designated, at the memory system, as a high priority memory space; (Talwar [0024] the memory network 100 may label a memory access request 301 with a particular priority level when the memory access request 301 stores, loads, or copies data to or from a target memory address within a particular memory address range. [0025] through identifying as elevated priority memory address ranges the portion of the shared memory 201 used by higher priority applications) (i.e., memory access request/command from high priority applications access memory address range designated as high priority memory space)
and use, in accordance with receiving the fourth commands, for the interleaving pattern, a highest priority of the plurality of priorities for the fourth commands instead of the fourth priority of the plurality of priorities. (Talwar [0025] the memory network 100 may determine an elevated priority for processing memory accesses when a target memory address specified in the memory access request 301 is within an elevated priority memory address range. Thus, the memory network 100 may employ a memory address-based labeling scheme. [0030] the memory network 100 may utilize a weighted round robin scheme) (i.e., elevated priority for processing a memory access that targets an memory address range with elevated priority means to use highest priority, instead of low priority, for the commands with highest priority)
Regarding Claim 10, Talwar teaches
The memory system of claim 1, wherein the interleaving pattern is in accordance with an interleaved round robin algorithm that is weighted using the first priority, the second priority, and the third priority. (Talwar [0030] The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme) (i.e., utilize a weighted round robin scheme is using an interleaving pattern, to process memory access request from queues associated with different priorities: the first priority, the second priority, and the third priority)
Regarding Claim 11, Talwar teaches
The memory system of claim 1, wherein the memory system comprises a plurality of memory spaces that comprises one or more logical units, one or more partitions, or both. (Talwar [0019] The shared memory 201 may be byte addressable and implement a memory addressing scheme such that the memory modules 221-225 respectively store data corresponding to a particular address range of the shared memory 201. Put another way, the shared memory 201 may implement a data space and a respective memory module may store a respective portion of the data space of the shared memory 201.) (i.e., the shared memory with address ranges implement data spaces, that is memory spaces comprises partitions)
Regarding Claim 12, Talwar teaches
The memory system of claim 1, wherein the interleaving pattern is configured to maintain a lower access throughput limit for memory spaces of the memory system. (Talwar [0044] In the second state, the monitoring system 600 may elevate the memory access priority level of an application, e.g., the particular application with a violated SLA requirement possibly caused by memory access contention for the shared memory 201 or in the memory network 100. Thus, in the second state, the memory network 100 may prioritize handling of memory access traffic for the affected application, e.g., via a weighted round robin arbitration of selection of queues 320 in the memory network 100 to process memory access requests.) (i.e., for application with a violated SLA requirement, use weighted round robin arbitration of selection of queues is using interleaving pattern to configure to maintain a minimum/lower throughput limit for the memory space that the application is associated with, to meet SLA requirement for the application)
Regarding Claim 13, Talwar teaches
The memory system of claim 1, wherein the second priority is different than the first priority, and the third priority is different than the first priority and the second priority. (Talwar [0024] Table 2, Example priority tiers for Memory-Address based labeling,
Priority Level P0, Priority Level P1, Priority Level P2) (i.e. priorities are different from each other)
Regarding Claim 14, Talwar teaches
A non-transitory, computer-readable medium storing code that comprises instructions executable by processing circuitry of a memory system to cause the memory system to: (Talwar [0011] prioritization of access to a memory shared by multiple devices, systems, compute nodes, applications, or other processing units. [0017] Memory address based prioritization of access to the shared memory [0055] The processor 810 may include a central processing unit (CPU), microprocessor, and/or any hardware device suitable for executing instructions stored on a computer-readable medium.)
receive a plurality of commands comprising first commands associated with a first memory space of the memory system that is assigned a first priority of a plurality of priorities, second commands associated with a second memory space of the memory system that is assigned a second priority of the plurality of priorities, and third commands associated with a third memory space of the memory system that is assigned a third priority of the plurality of priorities; (Talwar [0012] FIG. 1, a memory network 100 that supports prioritizing access to a shared memory. [0015] The memory network 100 may govern access to the shared memory by multiple compute nodes. In that regard, the memory network 100 may route memory access requests received from multiple compute nodes to a corresponding portion of the shared memory. [0024] the memory network 100 labels memory access traffic according to memory address range. Memory accesses targeting data with a particular memory address range (or ranges) in the shared memory 201 may be associated with a particular priority level…accesses to a first memory address range in the shared memory 201 may be assigned an elevated (e.g., high) priority level whereas accesses to a second memory address range in the shared memory 201 may be assigned a non-elevated or lower (e.g., normal) priority level.) (i.e., memory address ranges with different priority level are memory spaces assigned different priorities, memory access requests/commands associated with different memory spaces are assigned different priorities)
and execute, in accordance with receiving the plurality of commands, the plurality of command using an interleaving pattern that is in accordance with the first priority, the second priority, and the third priority. (Talwar [0030] Upon determining a priority level for the memory access request 301, the memory network 100 may process the memory access request 301 according to the determined priority level. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme) (i.e., utilize a weighted round robin scheme is using an interleaving pattern)
Regarding Claim 15, Talwar teaches
store, in accordance with receiving the plurality of commands, the plurality of commands into a queue, (Talwar [0030] The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301.)
wherein an order of the plurality of commands in the queue is using the interleaving pattern, (Talwar [0030] In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may utilize a weighted round robin scheme, weighted fair queuing scheme, or any bandwidth share scheme to dequeue access requests from the queues 320 to process)
and wherein the plurality of commands are executed using the order of the plurality of commands in the queue. (Talwar [0030] dequeuing memory access requests from the queues 320 for processing)
Regarding Claim 16, Talwar teaches
receive, in accordance with receiving the plurality of commands, fourth commands of the plurality of commands associated with a fourth memory space that is assigned a fourth priority of the plurality of priorities and is designated, at the memory system, as a high priority memory space; (Talwar [0024] the memory network 100 may label a memory access request 301 with a particular priority level when the memory access request 301 stores, loads, or copies data to or from a target memory address within a particular memory address range. [0025] through identifying as elevated priority memory address ranges the portion of the shared memory 201 used by higher priority applications) (i.e., memory access request/command from high priority applications access memory address range designated as high priority memory space)
and use, in accordance with receiving the fourth commands, for the interleaving pattern, a highest priority of the plurality of priorities for the fourth commands instead of the fourth priority of the plurality of priorities. (Talwar [0025] the memory network 100 may determine an elevated priority for processing memory accesses when a target memory address specified in the memory access request 301 is within an elevated priority memory address range. Thus, the memory network 100 may employ a memory address-based labeling scheme. [0030] the memory network 100 may utilize a weighted round robin scheme) (i.e., elevated priority for processing a memory access that targets an memory address range with elevated priority means to use highest priority, instead of low priority, for the commands with highest priority)
Regarding Claim 21, Talwar teaches
A method by a memory system, comprising: (Talwar [0011] prioritization of access to a memory shared by multiple devices, systems, compute nodes, applications, or other processing units. [0017] Memory address based prioritization of access to the shared memory)
receive a plurality of commands comprising first commands associated with a first memory space of the memory system that is assigned a first priority of a plurality of priorities, second commands associated with a second memory space of the memory system that is assigned a second priority of the plurality of priorities, and third commands associated with a third memory space of the memory system that is assigned a third priority of the plurality of priorities; (Talwar [0012] FIG. 1, a memory network 100 that supports prioritizing access to a shared memory. [0015] The memory network 100 may govern access to the shared memory by multiple compute nodes. In that regard, the memory network 100 may route memory access requests received from multiple compute nodes to a corresponding portion of the shared memory. [0024] the memory network 100 labels memory access traffic according to memory address range. Memory accesses targeting data with a particular memory address range (or ranges) in the shared memory 201 may be associated with a particular priority level…accesses to a first memory address range in the shared memory 201 may be assigned an elevated (e.g., high) priority level whereas accesses to a second memory address range in the shared memory 201 may be assigned a non-elevated or lower (e.g., normal) priority level.) (i.e., memory address ranges with different priority level are memory spaces assigned different priorities, memory access requests/commands associated with different memory spaces are assigned different priorities)
and execute, in accordance with receiving the plurality of commands, the plurality of command using an interleaving pattern that is in accordance with the first priority, the second priority, and the third priority. (Talwar [0030] Upon determining a priority level for the memory access request 301, the memory network 100 may process the memory access request 301 according to the determined priority level. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme) (i.e., utilize a weighted round robin scheme is using an interleaving pattern)
Regarding Claim 22, Talwar teaches
storing, in accordance with receiving the plurality of commands, the plurality of commands into a queue, (Talwar [0030] The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301.)
wherein an order of the plurality of commands in the queue is using the interleaving pattern, (Talwar [0030] In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may utilize a weighted round robin scheme, weighted fair queuing scheme, or any bandwidth share scheme to dequeue access requests from the queues 320 to process)
and wherein the plurality of commands are executed using the order of the plurality of commands in the queue. (Talwar [0030] dequeuing memory access requests from the queues 320 for processing)
Regarding Claim 23, Talwar teaches
receiving, in accordance with receiving the plurality of commands, fourth commands of the plurality of commands associated with a fourth memory space that is assigned a fourth priority of the plurality of priorities and is designated, at the memory system, as a high priority memory space; (Talwar [0024] the memory network 100 may label a memory access request 301 with a particular priority level when the memory access request 301 stores, loads, or copies data to or from a target memory address within a particular memory address range. [0025] through identifying as elevated priority memory address ranges the portion of the shared memory 201 used by higher priority applications) (i.e., memory access request/command from high priority applications access memory address range designated as high priority memory space)
and using, in accordance with receiving the fourth commands, for the interleaving pattern, a highest priority of the plurality of priorities for the fourth commands instead of the fourth priority of the plurality of priorities. (Talwar [0025] the memory network 100 may determine an elevated priority for processing memory accesses when a target memory address specified in the memory access request 301 is within an elevated priority memory address range. Thus, the memory network 100 may employ a memory address-based labeling scheme. [0030] the memory network 100 may utilize a weighted round robin scheme) (i.e., elevated priority for processing a memory access that targets an memory address range with elevated priority means to use highest priority, instead of low priority, for the commands with highest priority)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6, 17, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talwar (US 20180004456), in view of Vogan (US 20140281050).
Regarding Claim 5, Talwar teaches
identify, in accordance with receiving the plurality of commands, while in a first mode for executing commands, that the plurality of commands are associated with a plurality of memory spaces, (Talwar [0024] the memory network 100 labels memory access traffic according to memory address range. Memory accesses targeting data with a particular memory address range (or ranges) in the shared memory 201 may be associated with a particular priority level.)
and activate, in accordance with the plurality of commands being associated with the plurality of memory spaces, a second mode for executing commands, wherein the plurality of commands are executed using the interleaving pattern in accordance with the second mode for executing commands being activated. (Talwar [0030] Upon determining a priority level for the memory access request 301, the memory network 100 may process the memory access request 301 according to the determined priority level. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme)
Talwar does not teach while in a first mode for executing commands, wherein commands are executed in an order of reception in accordance with the first mode for executing commands being activated; and activate, a second mode for executing commands, in accordance with the second mode for executing commands being activated.
However, Vogan teaches while in a first mode for executing commands, wherein commands are executed in an order of reception in accordance with the first mode for executing commands being activated; (Vogan [0005] a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile electrically erasable semiconductor memory. The mode selector selects from a set of storage processor operation modes including a standard mode and a preemption mode. [0008] storage processor operational modes include a standard operational mode, in which the storage processor addresses each available queue sequentially, and handles the request) (i.e., standard operational mode is the first mode)
and activate, a second mode for executing commands, in accordance with the second mode for executing commands being activated. (Vogan [0010] the storage processor includes a mode selector, the mode selector selects the pre-emption mode if the depth of a queue grows beyond a certain size) (i.e., pre-emption mode is the second mode)
Talwar and Vogan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Talwar and Vogan to modify the Talwar‘s address based prioritization of memory access with Vogan’s teaching of a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile memory using two storage processor operation modes. The motivation for doing so would be for managing priority based Input Output (I/O) command queuing based on system conditions (Vogan [0005-0007]).
Regarding Claim 6, Talwar and Vogan teach
Talwar does not teach but Vogan teaches wherein the processing circuitry is further configured to cause the memory system to: identify, in accordance with receiving the plurality of commands, that a quantity of the plurality of commands in a queue is greater than a threshold, wherein the second mode for executing commands is activated in accordance with the quantity of the plurality of commands in the queue being greater than the threshold. (Vogan [0006] as memory access requests are received by the command interface, they are placed in a queue associated with the external priority of the request [0010] the storage processor includes a mode selector, the mode selector selects the pre-emption mode if the depth of a queue grows beyond a certain size) (i.e., pre-emption mode is the second mode)
Talwar and Vogan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Talwar and Vogan to modify the Talwar‘s address based prioritization of memory access with Vogan’s teaching of a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile memory using two storage processor operation modes. The motivation for doing so would be for managing priority based Input Output (I/O) command queuing based on system conditions (Vogan [0005-0007]).
Regarding Claim 17, Talwar teaches
identify, in accordance with receiving the plurality of commands, while in a first mode for executing commands, that the plurality of commands are associated with a plurality of memory spaces, (Talwar [0024] the memory network 100 labels memory access traffic according to memory address range. Memory accesses targeting data with a particular memory address range (or ranges) in the shared memory 201 may be associated with a particular priority level.)
and activate, in accordance with the plurality of commands being associated with the plurality of memory spaces, a second mode for executing commands, wherein the plurality of commands are executed using the interleaving pattern in accordance with the second mode for executing commands being activated. (Talwar [0030] Upon determining a priority level for the memory access request 301, the memory network 100 may process the memory access request 301 according to the determined priority level. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme)
Talwar does not teach while in a first mode for executing commands, wherein commands are executed in an order of reception in accordance with the first mode for executing commands being activated; and activate, a second mode for executing commands, in accordance with the second mode for executing commands being activated.
However, Vogan teaches while in a first mode for executing commands, wherein commands are executed in an order of reception in accordance with the first mode for executing commands being activated; (Vogan [0005] a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile electrically erasable semiconductor memory. The mode selector selects from a set of storage processor operation modes including a standard mode and a preemption mode. [0008] storage processor operational modes include a standard operational mode, in which the storage processor addresses each available queue sequentially, and handles the request) (i.e., standard operational mode is the first mode)
and activate, a second mode for executing commands, in accordance with the second mode for executing commands being activated. (Vogan [0010] the storage processor includes a mode selector, the mode selector selects the pre-emption mode if the depth of a queue grows beyond a certain size) (i.e., pre-emption mode is the second mode)
Talwar and Vogan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Talwar and Vogan to modify the Talwar‘s address based prioritization of memory access with Vogan’s teaching of a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile memory using two storage processor operation modes. The motivation for doing so would be for managing priority based Input Output (I/O) command queuing based on system conditions (Vogan [0005-0007]).
Regarding Claim 24, Talwar teaches
identifying, in accordance with receiving the plurality of commands, while in a first mode for executing commands, that the plurality of commands are associated with a plurality of memory spaces, (Talwar [0024] the memory network 100 labels memory access traffic according to memory address range. Memory accesses targeting data with a particular memory address range (or ranges) in the shared memory 201 may be associated with a particular priority level.)
and activating, in accordance with the plurality of commands being associated with the plurality of memory spaces, a second mode for executing commands, wherein the plurality of commands are executed using the interleaving pattern in accordance with the second mode for executing commands being activated. (Talwar [0030] Upon determining a priority level for the memory access request 301, the memory network 100 may process the memory access request 301 according to the determined priority level. The memory network 100 may buffer a particular memory access request 301 to the particular queue among the queues 320 associated with a determined priority for the request 301. In dequeuing memory access requests from the queues 320 for processing, the memory network 100 may employ an arbitration scheme to select which of the queues 320 to process a memory access request from…the memory network 100 may utilize a weighted round robin scheme)
Talwar does not teach while in a first mode for executing commands, wherein commands are executed in an order of reception in accordance with the first mode for executing commands being activated; and activating, a second mode for executing commands, in accordance with the second mode for executing commands being activated.
However, Vogan teaches while in a first mode for executing commands, wherein commands are executed in an order of reception in accordance with the first mode for executing commands being activated; (Vogan [0005] a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile electrically erasable semiconductor memory. The mode selector selects from a set of storage processor operation modes including a standard mode and a preemption mode. [0008] storage processor operational modes include a standard operational mode, in which the storage processor addresses each available queue sequentially, and handles the request) (i.e., standard operational mode is the first mode)
and activating, a second mode for executing commands, in accordance with the second mode for executing commands being activated. (Vogan [0010] the storage processor includes a mode selector, the mode selector selects the pre-emption mode if the depth of a queue grows beyond a certain size) (i.e., pre-emption mode is the second mode)
Talwar and Vogan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Talwar and Vogan to modify the Talwar‘s address based prioritization of memory access with Vogan’s teaching of a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile memory using two storage processor operation modes. The motivation for doing so would be for managing priority based Input Output (I/O) command queuing based on system conditions (Vogan [0005-0007]).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Velusamy (US 20190347039) teaches round robin system with interleaved weighted and priority arbiters to serve on-demand bandwidth of a storage system.
Zhang (CN114385370B) teaches presetting shared memory space and configuring the sizes and priorities.
Conclusion
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