DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statement (IDS) submitted on 09/03/2025, 09/03/2025, 09/03/2025, 09/03/2025, 09/03/2025, 09/03/2025, 10/27/2025, 01/05/2026, 02/26/2026 and 06/05/2026 are being considered by the examiner.
It is desirable to avoid the submission of long lists of documents if it can be avoided. Clearly irrelevant and marginally pertinent cumulative information should be
eliminated. If a long list is submitted, those documents which have been specifically
brought to applicant's attention and/or are known to be of most significance should be
highlighted. See Penn Yan Boats, Inc. v. Sea Lark Boats, Inc., 359 F. Supp. 948, 175
USPQ 260 (S.D. Fla. 1972), aff'd, 479 F.2d 1338, 178 USPQ 577 (5th Cir. 1973), cert.
denied, 414 U.S. 874 (1974). But cf. Molins PLC v. Textron Inc., 48 F.3d 1172, 33
USPQ2d 1823 (Fed. Cir. 1995). See MPEP 2004.
Applicant's duty of disclosure of material and information is not satisfied by
presenting a patent examiner with a mountain of largely irrelevant [material] from which
he is presumed to have been able, with his expertise and with adequate time, to have
found the critical [material]. It ignores the real world conditions under which examiners
work. See Rohm & Haas Co. v. Crystal Chemical Co., 722 F.2d 1556, 1573 [220 USPQ
289] (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984). (Emphasis in original).
Applicant has a duty not just to disclose pertinent prior art references but to make a disclosure in such way as not to “bury” it within other disclosures of less relevant prior
art; See Golden Valley Microwave Foods Inc. v. Weaver Popcorn Co. Inc., 24 USPQ2d
1801 (N.D. Ind. 1992); Molins PLC v. Textron Inc., 26 USPQ2d 1889, at 1899 (D.Del
1992); Penn Yan Boats, Inc. v. Sea Lark Boats, Inc. et al., 175 USPQ 260, at 272 (S.D.
Fl. 1972).
Claim Status
Claims 1-20 are pending
Claims 4-10 and 17-20 are objected to
Claims 1-3 and 11-16 are rejected under 35 USC § 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 14, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN; YOUNG MIN (US 20150161047 A1)[Shin] in view of Noguchi; Hiroki et al. (US 10360151 B2)[Noguchi] in view of WANG, SHU-MING et al. (CN 109408445 A)[Wang]
Regarding claim 1 Shin discloses: A graphics processor comprising: an interface to a host processor (Shin [0059], Fig. 6: teaches multi-core CPU system 100 transmitting or receiving data to or from the external memory 220 and the wireless interface block 240 through the interface block 210. The interface block 210 includes a memory controller that controls the external memory 220); a memory interface (Shin [0059], Fig. 6: teaches interface block 210); [a processing array including a plurality of graphics processing resources, the processing array coupled with a memory via the memory interface]; a cache memory coupled with the plurality of graphics processing resources, wherein the cache memory is a single level of a cache memory hierarchy and includes multiple memory regions having different capacities and latencies (Shin:[0008]: teaches a shared L2 cache including a plurality of L2 cache regions, and a size adjusting circuit allocating at least one region among the plurality of L2 cache regions to the operating cores based upon latency between each of the plurality of L2 cache regions and the operating cores. The size adjusting circuit adjusts the size of the shared L2 cache based on distances between the shared L2 cache and each of the plurality of cores. Shin [0007]: teaches According to an exemplary embodiment, when the shared L2 cache includes a plurality of L2 cache regions, the size adjusting circuit may control each power supplied to each of the plurality of L2 cache regions so as to adjust the size of the shared L2 cache. When the shared L2 cache includes a plurality of L2 cache regions, the size adjusting circuit may control connections among the plurality of L2 cache regions so as to adjust the size of the shared L2 cache. Adjusting size of the shared L2 cache based on distance to cores implies having l2 cache regions with different size/capacity. Shin [0004]: teaches as the size (or capacity) of the L2 cache increases, the latency of a core accessing the L2 cache also increases. The size of the L2 cache increases as the number of cores increases, so that the latency of each core accessing the L2 cache also increases. So, latency is different for different region.); and [a cache controller associated with the cache memory, the cache controller including region selection circuitry to select between the multiple memory regions to store a cached unit of data].
Shin teaches a cache having multiple memory regions and memory interface. However, Shin did not explicitly talk about region selection logic/circuit.
Noguchi discloses:
a cache controller associated with the cache memory, the cache controller including region selection circuitry to select between the multiple memory regions to store a cached unit of data (Noguchi: Col5/ln56-col5/ln67, (44): teaches the L2 cache 5 functions as a region selection unit (region switch) which writes data into the high-speed region or the low-speed region. Noguchi: Col2/ln47-col2/ln52, (16): teaches the L2 cache 5 including an L2 cache controller 12 including a way number control unit (way allocation controller) 14.).
Noguchi also discloses:
a cache memory coupled with the plurality of graphics processing resources, wherein the cache memory is a single level of a cache memory hierarchy and includes multiple memory regions having different capacities and latencies (Noguchi: Col1/ln66-col2/ln7,(8): teaches a cache memory system having a first cache memory, a second cache memory which comprises a plurality of regions having different access speeds (latencies) and a cache controller which carries out a control where data to be stored in the second cache memory is sorted to the plurality of regions and stored thereto in accordance with access conditions with respect to the first cache memory. Noguchi: Col6/ln11-col6/ln18,(46): The memory capacity of the high-speed region and the low-speed region inside the L2 cache 5 can be made changeable in accordance with access conditions. This indicates that the capacity of different region is different.);
Both Shin and Noguchi represent works within the same field of endeavor, namely information processing devices focusing on storage systems. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Shin in view of Noguchi as it represents a combination of known prior art elements according to known methods (multi-region cache memory system of Shin using multi-region selector as used in Noguchi) to yield a more efficient storage system resulting in a more efficient computing system (see also Noguchi Col1/ln66-col2/ln7,(8), Col2/ln47-col2/ln52, (16), Col5/ln56-col5/ln67, (44), Col6/ln11-col6/ln18,(46)).
Shin/Noguchi teaches multi-region cache system with selector logic to select memory regions and the cache system is coupled with multiple processors. However, Shin/Noguchi did not explicitly disclose multiple processors being graphics processors.
Wang discloses:
a processing array including a plurality of graphics processing resources, the processing array coupled with a memory via the memory interface (Wang abstract: teaches field programmable gate array connected to the plurality of graphics processor unit by the control signal. According to the control signal to logic control a plurality of graphics processor unit, a connector through the PCIE bus connecting to a plurality of graphic processor unit and a field programmable gate array.);
Both Shin/Noguchi and Wang represent works within the same field of endeavor, namely information processing devices focusing on storage systems. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Shin/Noguchi in view of Wang as it represents a combination of known prior art elements according to known methods (multi-region cache memory system of Shin/Noguchi using plurality of graphics processor as used in Wang) to yield a more efficient storage system resulting in a more efficient computing system (see also Wang abstract).
Regarding claim 2 Shin/Noguchi/Wang discloses: The graphics processor of claim 1, wherein the multiple memory regions include a near region and a far region and the near region has a lower capacity and lower latency relative to the far region (Noguchi Col2/ln57-col2/ln67, (18): The L2 data memory includes, as mentioned later, a high-speed region capable of high-speed access and a low-speed region with access speed lower than that of the high-speed region. The high-speed region and the low-speed region each may be allocated to fixed dispositions inside the L2 data memory. Alternatively, the dispositions of the high-speed region and the low-speed region may be made shiftable inside the L2 data memory. Furthermore, as mentioned later, memory sizes of the high-speed region and the low-speed region may be controlled so as to change the sizes arbitrarily. Noguchi col1/ln21-col1/ln31, (3): teaches access speed and memory capacity have a trade-off relationship. Increase in the memory capacity lowers the access speed, while decrease in the memory capacity improves the access speed. The high speed region is similar to near region with low latency and the low speed region is similar to far region with higher latency).
Regarding claim 3 Shin/Noguchi/Wang discloses: The graphics processor of claim 2, wherein the region selection circuitry is configured to store the cached unit of data to the near region or the far region based on usage metrics associated with the cached unit of data (Noguchi Col5/ln30-col5/ln40, (40), FIG. 5: teaches the L2 cache controller 12 determining whether the measurement value of the L1 reference frequency counter 9 exceeds a predetermined threshold (step S21). When determined that the measurement value is exceeding the threshold, data to be written is stored in the high-speed region (step S22). The L1 reference frequency counter is a type of usage metrics because it counts the reference/access frequency and high speed region is similar to near region).
Regarding claim 14 Shin discloses: A graphics processing system comprising: a memory device (Shin [0059], Fig. 6: teaches multi-core CPU system 100 transmitting or receiving data to or from the external memory 220); and an accelerator coupled with the memory device, the accelerator including: an interface to a host processor (Shin [0059], Fig. 6: teaches multi-core CPU system 100 transmitting or receiving data to or from the external memory 220 and the wireless interface block 240 through the interface block 210. The interface block 210 includes a memory controller that controls the external memory 220); a memory interface (Shin [0059], Fig. 6: teaches multi-core CPU system 100 transmitting or receiving data to or from the external memory 220 and the wireless interface block 240 through the interface block 210. The interface block 210 includes a memory controller that controls the external memory 220) [to the memory device, a processing array including a plurality of graphics processing resources]; a cache memory coupled with the plurality of graphics processing resources, wherein the cache memory is a single level of a cache memory hierarchy and includes multiple memory regions having different capacities and latencies (Shin:[0008]: teaches a shared L2 cache including a plurality of L2 cache regions, and a size adjusting circuit allocating at least one region among the plurality of L2 cache regions to the operating cores based upon latency between each of the plurality of L2 cache regions and the operating cores. The size adjusting circuit adjusts the size of the shared L2 cache based on distances between the shared L2 cache and each of the plurality of cores. Shin [0007]: teaches According to an exemplary embodiment, when the shared L2 cache includes a plurality of L2 cache regions, the size adjusting circuit may control each power supplied to each of the plurality of L2 cache regions so as to adjust the size of the shared L2 cache. When the shared L2 cache includes a plurality of L2 cache regions, the size adjusting circuit may control connections among the plurality of L2 cache regions so as to adjust the size of the shared L2 cache. Adjusting size of the shared L2 cache based on distance to cores implies having l2 cache regions with different size/capacity. Shin [0004]: teaches as the size (or capacity) of the L2 cache increases, the latency of a core accessing the L2 cache also increases. The size of the L2 cache increases as the number of cores increases, so that the latency of each core accessing the L2 cache also increases. So, latency is different for different region); and [a cache controller associated with the cache memory, the cache controller including region selection circuitry to select between the multiple memory regions to store a cached unit of data].
Shin teaches a cache having multiple memory regions and memory interface. However, Shin did not explicitly talk about region selection logic/circuit.
Noguchi discloses:
a cache controller associated with the cache memory, the cache controller including region selection circuitry to select between the multiple memory regions to store a cached unit of data (Noguchi: Col5/ln56-col5/ln67, (44): teaches the L2 cache 5 functions as a region selection unit (region switch) which writes data into the high-speed region or the low-speed region. Noguchi: Col2/ln47-col2/ln52, (16): teaches the L2 cache 5 including an L2 cache controller 12 including a way number control unit (way allocation controller) 14.).
Noguchi also discloses:
a cache memory coupled with the plurality of graphics processing resources, wherein the cache memory is a single level of a cache memory hierarchy and includes multiple memory regions having different capacities and latencies (Noguchi: Col1/ln66-col2/ln7,(8): teaches a cache memory system having a first cache memory, a second cache memory which comprises a plurality of regions having different access speeds (latencies) and a cache controller which carries out a control where data to be stored in the second cache memory is sorted to the plurality of regions and stored thereto in accordance with access conditions with respect to the first cache memory. Noguchi: Col6/ln11-col6/ln18,(46): The memory capacity of the high-speed region and the low-speed region inside the L2 cache 5 can be made changeable in accordance with access conditions. This indicates that the capacity of different region is different.);
Both Shin and Noguchi represent works within the same field of endeavor, namely information processing devices focusing on storage systems. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Shin in view of Noguchi as it represents a combination of known prior art elements according to known methods (multi-region cache memory system of Shin using multi-region selector as used in Noguchi) to yield a more efficient storage system resulting in a more efficient computing system (see also Noguchi Col1/ln66-col2/ln7,(8), Col2/ln47-col2/ln52, (16), Col5/ln56-col5/ln67, (44), Col6/ln11-col6/ln18,(46)).
Shin/Noguchi teaches multi-region cache system with selector logic to select memory regions and the cache system is coupled with multiple processors. However, Shin/Noguchi did not explicitly disclose multiple processors being graphics processors.
Wang discloses:
a processing array including a plurality of graphics processing resources (Wang abstract: teaches field programmable gate array connected to the plurality of graphics processor unit by the control signal. According to the control signal to logic control a plurality of graphics processor unit, a connector through the PCIE bus connecting to a plurality of graphic processor unit and a field programmable gate array.);
Both Shin/Noguchi and Wang represent works within the same field of endeavor, namely information processing devices focusing on storage systems. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Shin/Noguchi in view of Wang as it represents a combination of known prior art elements according to known methods (multi-region cache memory system of Shin/Noguchi using plurality of graphics processor as used in Wang) to yield a more efficient storage system resulting in a more efficient computing system (see also Wang abstract).
Regarding claim 15 Shin/Noguchi/Wang discloses: The graphics processing system of claim 14, wherein the multiple memory regions include a near region and a far region and the near region has a lower capacity and lower latency relative to the far region (Noguchi Col2/ln57-col2/ln67, (18): The L2 data memory includes, as mentioned later, a high-speed region capable of high-speed access and a low-speed region with access speed lower than that of the high-speed region. The high-speed region and the low-speed region each may be allocated to fixed dispositions inside the L2 data memory. Alternatively, the dispositions of the high-speed region and the low-speed region may be made shiftable inside the L2 data memory. Furthermore, as mentioned later, memory sizes of the high-speed region and the low-speed region may be controlled so as to change the sizes arbitrarily. Noguchi col1/ln21-col1/ln31, (3): teaches access speed and memory capacity have a trade-off relationship. Increase in the memory capacity lowers the access speed, while decrease in the memory capacity improves the access speed. The high speed region is similar to near region with low latency and the low speed region is similar to far region with higher latency).
Regarding claim 16 Shin/Noguchi/Wang discloses: The graphics processing system of claim 15, wherein the region selection circuitry is configured to store the cached unit of data to the near region or the far region based on usage metrics associated with the cached unit of data (Noguchi Col5/ln30-col5/ln40, (40), FIG. 5: teaches the L2 cache controller 12 determining whether the measurement value of the L1 reference frequency counter 9 exceeds a predetermined threshold (step S21). When determined that the measurement value is exceeding the threshold, data to be written is stored in the high-speed region (step S22). The L1 reference frequency counter is a type of usage metrics because it counts the reference/access frequency and high speed region is similar to near region).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN; YOUNG MIN (US 20150161047 A1)[Shin] in view of Noguchi; Hiroki et al. (US 10360151 B2)[Noguchi] in view of Fujita; Ryo et al. (US 5666520 A)[Fujita]
Regarding claim 11 Shin discloses: A method comprising: [receiving data at a graphics processor from a host processor via an interface to the host processor] storing received data in a cache memory, wherein the cache memory is a single level of a cache memory hierarchy and includes multiple memory regions having different capacities and latencies (Shin:[0008]: teaches a shared L2 cache including a plurality of L2 cache regions, and a size adjusting circuit allocating at least one region among the plurality of L2 cache regions to the operating cores based upon latency between each of the plurality of L2 cache regions and the operating cores. The size adjusting circuit adjusts the size of the shared L2 cache based on distances between the shared L2 cache and each of the plurality of cores. Shin [0007]: teaches According to an exemplary embodiment, when the shared L2 cache includes a plurality of L2 cache regions, the size adjusting circuit may control each power supplied to each of the plurality of L2 cache regions so as to adjust the size of the shared L2 cache. When the shared L2 cache includes a plurality of L2 cache regions, the size adjusting circuit may control connections among the plurality of L2 cache regions so as to adjust the size of the shared L2 cache. Adjusting size of the shared L2 cache based on distance to cores implies having l2 cache regions with different size/capacity. Shin [0004]: teaches as the size (or capacity) of the L2 cache increases, the latency of a core accessing the L2 cache also increases. The size of the L2 cache increases as the number of cores increases, so that the latency of each core accessing the L2 cache also increases. So, latency is different for different region.); and [selecting a memory region from the multiple memory regions to store a cached unit of data; accessing the cached unit of data from a selected memory region; and performing a processing operation based on the cached unit of data via a processing resource of the graphics processor]
Shin teaches a cache having multiple memory regions. However, Shin did not explicitly talk about region selection logic/circuit.
Noguchi discloses:
selecting a memory region from the multiple memory regions to store a cached unit of data (Noguchi: Col5/ln56-col5/ln67, (44): teaches the L2 cache 5 functions as a region selection unit (region switch) which writes data into the high-speed region or the low-speed region);
accessing the cached unit of data from a selected memory region (Noguchi: col6/ln1-col6/ln10, (45) FIG. 6: teaches determining whether data is stored in the high-speed region (step S31). If the data is stored in the high-speed region, the data moves to the low-speed region after transferring/accessing the data to the L1 cache 4 (step S32). If the data is determined in step S31 that it is stored in the low-speed region, the data is transferred/accessed to the L1 cache 4);
Noguchi also discloses:
storing received data in a cache memory, wherein the cache memory is a single level of a cache memory hierarchy and includes multiple memory regions having different capacities and latencies (Noguchi: Col1/ln66-col2/ln7,(8): teaches a cache memory system having a first cache memory, a second cache memory which comprises a plurality of regions having different access speeds (latencies) and a cache controller which carries out a control where data to be stored in the second cache memory is sorted to the plurality of regions and stored thereto in accordance with access conditions with respect to the first cache memory. Noguchi: Col6/ln11-col6/ln18,(46): The memory capacity of the high-speed region and the low-speed region inside the L2 cache 5 can be made changeable in accordance with access conditions. This indicates that the capacity of different region is different.);
Both Shin and Noguchi represent works within the same field of endeavor, namely information processing devices focusing on storage systems. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Shin in view of Noguchi as it represents a combination of known prior art elements according to known methods (multi-region cache memory system of Shin using multi-region selector as used in Noguchi) to yield a more efficient storage system resulting in a more efficient computing system (see also Noguchi Col1/ln66-col2/ln7,(8), Col2/ln47-col2/ln52, (16), Col5/ln56-col5/ln67, (44), Col6/ln11-col6/ln18,(46)).
Shin/Noguchi teaches multi-region cache system with selector logic to select memory regions and the cache system is coupled with multiple processors. However, Shin/Noguchi did not explicitly disclose receiving data at a graphics processors from host and perform processing operation.
Fujita discloses:
receiving data at a graphics processor from a host processor via an interface to the host processor (Fujita: col5/ln22-col5/ln33, (3), FIG. 2: teaches a host processor 1 to execute these programs and send/receive graphic data to/from a graphic processor 3 and a graphic processor 3 converting graphic data to pixel data and write and read data in/from a frame memory 4 according to the instructions from the host processor);
performing a processing operation based on the cached unit of data via a processing resource of the graphics processor (Fujita: col5/ln22-col5/ln33, (3), FIG. 2: teaches a host processor 1 to execute these programs and send/receive graphic data to/from a graphic processor 3 and a graphic processor 3 converting graphic data to pixel data and write and read data in/from a frame memory 4 according to the instructions from the host processor).
Both Shin/Noguchi and Fujita represent works within the same field of endeavor, namely information processing devices focusing on storage systems. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Shin/Noguchi in view of Fujita as it represents a combination of known prior art elements according to known methods (multi-region cache memory system of Shin/Noguchi using graphics processor as used in Fujita) to yield a more efficient storage system resulting in a more efficient computing system (see also Fujita col5/ln22-col5/ln33, (3), FIG. 2 ).
Regarding claim 12 Shin/Noguchi/Fujita discloses: The method of claim 11, wherein the multiple memory regions include a near region and a far region and the near region has a lower capacity and lower latency relative to the far region (Noguchi Col2/ln57-col2/ln67, (18): The L2 data memory includes, as mentioned later, a high-speed region capable of high-speed access and a low-speed region with access speed lower than that of the high-speed region. The high-speed region and the low-speed region each may be allocated to fixed dispositions inside the L2 data memory. Alternatively, the dispositions of the high-speed region and the low-speed region may be made shiftable inside the L2 data memory. Furthermore, as mentioned later, memory sizes of the high-speed region and the low-speed region may be controlled so as to change the sizes arbitrarily. Noguchi col1/ln21-col1/ln31, (3): teaches access speed and memory capacity have a trade-off relationship. Increase in the memory capacity lowers the access speed, while decrease in the memory capacity improves the access speed. The high speed region is similar to near region with low latency and the low speed region is similar to far region with higher latency).
Regarding claim 13 Shin/Noguchi/Fujita discloses: The method of claim 12, comprising selecting the memory region to store the cached unit of data based on usage metrics associated with the cached unit of data (Noguchi Col5/ln30-col5/ln40, (40), FIG. 5: teaches the L2 cache controller 12 determining whether the measurement value of the L1 reference frequency counter 9 exceeds a predetermined threshold (step S21). When determined that the measurement value is exceeding the threshold, data to be written is stored in the high-speed region (step S22). The L1 reference frequency counter is a type of usage metrics because it counts the reference/access frequency and high speed region is similar to near region).
Allowable Subject Matter
Claims 4-10 and 17-20 are being objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 recites, ‘The graphics processor of claim 3, wherein the region selection circuitry is configured to store the cached unit of data to the near region or the far region based on a hint associated with the cached unit of data’.
Prior art Kolovson [0043-0047] FIG. 6-8: teaches the storage controller executes one or more operations to manage cache memory resources in accordance with the cache hints associated with the data operation request. Teaches a Write Through Cache hint associated with a data operation and storage controller executes a fast de-stage of data associated with the Write Through Cache hint to permanent media (e.g., to a disk array). A Write Through Cache hint identifies data associated with the operation by logical unit number (LUN). Also teaches a Pin Cache hint and the data remains "pinned" in cache until an Unpin Cache hint.
Prior art ARIMILLI; RAVI K. et al. (US 20090198903 A1)[Arimilli] [0044]: teaches a load instruction within the program code being associated with a hint. After detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
Prior art Moyer; Paul (US 20180143911 A1)[Moyer] [0012]: teaches a cache having two test regions and a non-test region, whereby all the regions are employed by the cache to store data in response to demand requests from a processor and in response to prefetch requests from a prefetcher. A cache controller receives demand requests and prefetch requests for data that are associated with software hints indicating when and how the data is to be stored in the cache. The cache controller employs different software hint policies for the different test regions, such that for one of the test regions the cache controller follows software hints associated with data. For the other test region, the cache controller ignores software hints associated with data. The processor monitors access metrics for each of the test regions, such as a cache hit rate, cache miss rate, or a combination thereof. Based on the access metrics, the processor selects the hint policy for one of the test regions and applies it to the non-test region of the cache. For example, if the cache hit rate is higher for one of the test regions, the processor applies the hint policy for that test region to the non-test region of the cache, thereby improving the hit rate for the cache overall.
Kolovson's cache hint is a Write Through Cache hint. Arimilli's cache hint is to load a partial cache line. Moyer's cache hint deals with demand and prefetch request that are associated with software hints indicating when and how the data is to be stored in the cache.
However, hint in instant claim is associated with the data and the hint is to select if the data should be stored in near region (high-speed/low-latency region) or far region (low-speed/high-latency region). No known prior art taken alone or in combination teaches region selection circuitry using hint associated with the cached unit of data to store the data to the near region (high-speed/low-latency region) or the far region (low-speed/high-latency region).
Claim 5-6 are dependent on claim 4 and is allowable due at least to this dependence.
Claim 7 is dependent on claim 6 and is allowable due at least to this dependence.
Claim 8 is dependent on claim 7 and is allowable due at least to this dependence.
Claim 9 is dependent on claim 8 and is allowable due at least to this dependence.
Claim 10 is dependent on claim 9 and is allowable due at least to this dependence.
Regarding claim 17, this is a graphics processing system claim corresponding to the graphics processor claim 4 and contains the same allowable claim limitation as in claim 4 and is allowable due to the same reason as mentioned above for claim 4.
Claim 18-19 are dependent on claim 17 and is allowable due at least to this dependence.
Claim 20 is dependent on claim 19 and is allowable due at least to this dependence.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is included in pe2e_search_notes and is attached as OA.APPENDIX.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD S HASAN whose telephone number is (571)270-1737. The examiner can normally be reached on Mon-Fri 8-5.
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/M.S.H/Examiner, Art Unit 2138
/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138 k we
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