DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-8, 15-16, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naruse et al (US 2005/0268130).
For claim 1, Naruse teaches a clock circuit improving frequency hopping (Figures 2-3), comprising:
a frequency divider (55, SEL1, Figure 3), configured for performing a frequency division (for CKI) according to a first divisor number (a division ratio of 1/16 is initially selected, [49]); and
a frequency hopping circuit coupled to the frequency divider (60), wherein:
when hopping to a frequency or a spread spectrum range corresponding to an input number (division ratio of 1/2, [49] and Figures 4 and 8), if a convergence condition (last frequency change point is reached, [60]) is not satisfied, the frequency hopping circuit is configured to perform a stepping operation (n=n+1, S7 of Figure 8, [60]) to update the first divisor number from a previous value to a current value which does not equal the input number (e.g., change division ratio from 1/16 to 1/8 or from 1/8 to 1/4, [49]).
For claim 2, Naruse further teaches:
if the convergence condition is satisfied, the frequency hopping circuit is configured to cause the first divisor number to equal the input number (as understood by examination of Figure 4).
For claim 4, Naruse further teaches:
whether the convergence condition is satisfied relates to whether an absolute difference between the input number and the first divisor number is less than a threshold value (smallest stepwise frequency change, e.g.,1/2, as understood by examination of the Figures).
For claim 5, Naruse further teaches:
each of the first divisor number and the threshold value is a non-integer value (fraction, as understood by examination of Figure 4);
the frequency hopping circuit is configured to represent the first divisor number and the threshold value by two binary values of a same number of bits (capable of since Naruse is implemented on a data processor and processors operate in binary, Abstract); and
a least significant bit of the binary value which represents the threshold value equals one, and remaining bits of the binary value which represents the threshold value equal zero (capable of since Naruse is implemented on a data processor and processors operate in binary, Abstract).
For claim 6, Naruse further teaches:
the frequency hopping circuit is further coupled to a hopping enabling signal (stb); and the frequency hopping circuit is configured to perform the stepping operation if the hopping enabling signal equals a predefined logic value (standby state is released) and the convergence condition is not satisfied ([52]).
For claim 7, Naruse further teaches:
if the hopping enabling signal does not equal the predefined logic value, the frequency hopping circuit is configured to cause the first divisor number to equal the input number ([52] and Figure 8).
For claim 8, Naruse further teaches:
when the frequency hopping circuit is configured to perform the stepping operation, if the input number is less than the previous value, the frequency hopping circuit is configured to cause the current value to equal the previous value minus a step value (S2-S7, Figure 4).
if the input number is greater than the previous value, the frequency hopping circuit is configured to cause the current value to equal the previous value plus the step value (S8-S9, Figure 8).
For claim 15, Naruse further teaches:
a facilitation circuit (50);
the facilitation circuit is coupled to the frequency divider, and configured to output a first clock to the frequency divider (as understood by examination of Figure 3); and
the frequency divider is configured to generate a second clock by performing the frequency division on the first clock (CKI).
For claim 16, Naruse further teaches:
the facilitation circuit is further configured to control timing of the first clock according to timing of the second clock (as understood by examination of Figure 3).
For claim 18, Naruse teaches a clock circuit improving frequency hopping (Figures 2-3), comprising:
a frequency divider (55, SEL1, Figure 3) configured to perform a frequency division (for CKI) according to a first divisor number (a division ratio of 1/16 is initially selected, [49]); and
a frequency hopping circuit coupled to the frequency divider (60) for providing the first divisor number (via the control input for SEL1); wherein:
the clock circuit is configured to provide a clock according to a result of the frequency division (CKI);
when the clock circuit is requested to cause a frequency of the clock to hop from a first frequency to a second frequency (division ratio of ½, [49] and Figures 4 and 8), the clock circuit is configured to stabilize the frequency of the clock to the second frequency after an interval (an interval corresponding to the last frequency change point being reached, [60]); and
the frequency hopping circuit is configured to stepwise change the first divisor number during the interval, such that, during the interval, the frequency of the clock does not fall after rising (n=n+1, S7 of Figure 8, [60]).
For claim 20, Naruse teaches a method applied to a clock circuit, wherein:
the clock circuit comprises a frequency divider (55, SEL1, Figure 3);
the frequency divider is configured to perform a frequency division according to a first divisor number (a division ratio of 1/16 is initially selected, [49]);
the clock circuit is configured to provide a clock according to a result of the frequency division (CKI);
the method comprises:
when causing the clock to hop to a frequency or a spread spectrum range corresponding to an input number (division ratio of ½, [49] and Figures 4 and 8), proceeding to a decision step to determine if a convergence condition is satisfied (last frequency change point is reached, [60] and Figure 8);
if the convergence condition is not satisfied, proceeding to a stepping step (S2-S7, Figure 8); and
if the convergence condition is satisfied, proceeding to a setting step (S8, Figure 8);
wherein the stepping step comprises:
updating the first divisor number from a previous value to a current value which does not equal the input number, and iterating the decision step (S7, Figure 8); and
wherein the setting step comprises:
causing the first divisor number to equal the input number (as understood by examination of Figures 4 and 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naruse in view of Wang (US 2010/0283549).
For claim 11, Naruse teaches the limitations of claim 1 but fails to teach a sigma delta modulator as claimed.
However, Wang teaches modifying a divisor value (N or N+1) according to an accumulated residue being greater or less than a threshold [23], thereby improving system stability [25].
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement Naruse’s dividers DIV1-DIV8 such that each divider has a corresponding sigma delta modulator in order to improve stability (Abstract, [25]).
The combination of Naruse and Wang as cited above teaches:
a sigma delta modulator (all of the sigma delta modulators corresponding to DIV1-DIV8) coupled between the frequency divider and the frequency hopping circuit;
the sigma delta modulator is configured to perform a sigma delta modulation on a sum of the first divisor number and a second divisor number (residue, [23]), and accordingly generate a modulated divisor number (N+1, [17], [23]); and when the frequency divider is configured to perform the frequency division according to the first divisor number, the frequency divider is configured to perform the frequency division according to the modulated divisor number (as understood by the combination of references).
For claim 17, Naruse teaches the limitations of claim 1 but fails to teach a detector, a filter and an oscillator as claimed.
It is noted that Naruse teaches a phase locked loop (50).
Examiner takes official notice that it is notoriously old and well known for phase locked loops to comprise a detector, filter and oscillator and perform the functionality as claimed as this merely relates to the standard model of a phase locked loop.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement Naruse’s phase locked loop (50) using a detector, filter and oscillator as claimed since the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
Allowable Subject Matter
Claims 3, 9-10, 12-14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shiao et al (US 2015/0171918) teaches a spread spectrum clock generator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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