DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 19/215,719 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statement 11/07/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is now directed to non-statutory subject.
As per the independent claims and their dependent claims respectively, they are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Paragraph 0093 of the filed specification and body of claims do not limit structural features to perform the steps. Rather, the body of the claims are interpreted as purely software because paragraph 0093 stated that the method can be performed by software. For example, paragraph 0109 discloses “a storage device 1240 coupled to communication infrastructure 1202 via a storage interface 1238. Storage device 1240 generally represents any type or form of storage device or medium capable of storing data and/or other computer-readable instructions”. Software is per se not a statutory class of invention. Therefore, the claims are rejected under 35 U.S.C. 101 because they are directed to software which is not a statutory class of invention.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-4, 7-15 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kachare et al. (US pub. 2020/0278796), hereinafter, “Kachare”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 12 and 20, Kachare discloses a system (see claim 19 of Kachare) comprising: a storage device configured to store data at logical block addresses (LBAs) [see paragraph 0062, which discloses “a solid state drive may include several different latency thresholds. The latency threshold may be specified, e.g., globally (i.e., a single latency threshold may apply to the entire solid state drive), per logical block address (LBA) range, or per namespace”]; and circuitry (see paragraph 0043) configured to: detect a latency of an input/output (I/O) transaction performed on a portion of the data stored at one of the LBAs (see paragraph 0053, which discloses “when a read command is received, in an act 410, by the solid state drive controller, it checks, in an act 415, whether the latency threshold bit is set in that command… The solid state drive controller periodically updates the timer, in an act 425, and checks the latency timer, in an act 430”); determine that the latency of the I/O transaction exceeds a certain threshold (see paragraph 0053, which discloses “when the solid state drive controller determines, in the act 430, that a read command has taken an amount of time exceeding the latency threshold”); and perform a remedial action in connection with the portion of data in response to determining that the latency of the I/O transaction exceeds the certain threshold [see paragraph 0053, which discloses “then the solid state drive 120 internally aborts the read command, in an act 435, and returns an error status code, referred to herein as a “latency threshold exceeded” error status code, to the host, in the command completion queue entry (or “command completion entry”) returned, in an act 440, to the host”].
3. As per claims 2 and 13, Kachare discloses “The system of claim 1” [See rejection to claim 1 above], wherein the circuitry is further configured to perform the remedial action by rewriting the portion of data to another one of the LBAs (see steps 510, 515 and 520 of fig. 5, showing access to the data in multiple SSDs).
4. As per claims 3 and 14, Kachare discloses wherein the circuitry is further configured to free a memory block of the storage device at the one of the LBAs by rewriting the portion of data (see steps 510, 515 and 520 of fig. 5, showing access to the data in multiple SSDs).
5. As per claims 4 and 15, Kachare discloses wherein the circuitry is further configured to recharge the freed memory block at the one of the LBAs to prepare the freed memory block for reallocation (see fig. 5).
6. As per claims 7 and 18, Kachare discloses wherein the circuitry is further configured to perform the remedial action by rewriting the portion of data to the one of the LBAs (see paragraph 0053).
7. As per claims 8 and 19, Kachare discloses wherein the circuitry is further configured to: monitor latencies of I/O transactions performed on the data stored at the LBAs; and dynamically set the certain threshold based at least in part on the latencies of the I/O transactions (see paragraphs 0048 and 0049).
8. As per claim 9, Kachare discloses wherein the circuitry is further configured to set the certain threshold to represent a permissible amount of time to complete I/O transactions (see paragraph 0048).
9. As per claim 10, Kachare discloses wherein the storage device comprises at least one of: a flash memory device; or a hard disk drive (see paragraph 0043).
10. As per claim 11, Kachare discloses wherein the I/O transaction comprises at least one of: a read operation; or a write operation (see paragraph 0053).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claims 5, 6, 16 and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kachare et al. (US pub. 2020/0278796), hereinafter, “Kachare”, in view of Martin et al. (US pat. 10/282,107), hereinafter, “Martin”.
13. As per claims 5 and 16, Kachare discloses “The system of claim 2” [See rejection to claim 1 above], fails to expressly discloses wherein the circuitry is further configured to perform the remedial action by: identifying a file to which the portion of data belongs; identifying an additional portion of the data that belongs to the file and is stored at an additional one of the LBAs; and rewriting the additional portion of data to the additional one of the LBAs or to another one of the LBAs.
Martin discloses wherein the circuitry is further configured to perform the remedial action by: identifying a file to which the portion of data belongs; identifying an additional portion of the data that belongs to the file and is stored at an additional one of the LBAs; and rewriting the additional portion of data to the additional one of the LBAs or to another one of the LBAs (see col. 10, lines 26-44).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Martin’s teaching of a method to control I/O response time to determine whether a first observed I/O response time for a storage group of one or more logical devices exceeds I/O performance specified by a service level objective, into Kachare’s teaching of a system for controlling read latency in a storage system that includes solid state drives, for the benefit of improving efficiency of response time for I/O transactions, making sure that the response time is less than a response time delay threshold.
14. As per claims 6 and 17, the combination of Kachare and Martin discloses “The system of claim 5” [See rejection to claim 5 above], wherein the circuitry is further configured to identify the file by: identifying metadata in a file system corresponding to the storage device; and determining that the portion of data belongs to the file based at least in part on the metadata (see col. 10, lines 26-44 of Martin).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
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