DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-9, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (USPN 10,979,058) in view of Quan et al. (USPN 8,390,355).
With respect to claim 1, Masuda et al. discloses, in Figs. 1, 2 and 5, a phase-locked loop (Fig. 1 details of lock detector and divider of Fig. 1 disclosed in Figs. 2 and 5) comprising:
a phase detection unit (22) configured to detect a phase difference between a first clock (REFCLK) and a second clock (FBCLK);
a voltage generation unit (23 with 24) configured to generate a control voltage (VCTL) in response to an output signal of the phase detection unit (UP/DN);
an oscillating unit (25) configured to generate a third clock that toggles at a frequency corresponding to a level of the control voltage (VCOCLK);
a clock division unit (26 details disclosed in Fig. 5) configured to generate a plurality of divided clocks (1/n and 1/(n+1) divided clocks, see Col. 6 lines 51-56) by dividing the third clock at a plurality of ratios (1/n and 1(/(n+1) ratios), and any one of the plurality of divided clocks that are output is selected as the second clock (FBCLOCK generated according to the selected frequency division ratio); and
a lock detection unit (41 of Fig. 2) configured to generate a first unlock signal (Q1) using the phase difference between the first and second clocks (difference based on REFCLK input to 53 and FBCLK input to 53 via 51) on the basis of a first phase difference corresponding to a cycle of a selected divided clock (the difference is on a basis of the cycle of the selected divide clock, since FBCLK input to 53 is based on the divided clock FBCLK which is the selected divided clock) and to generate a second unlock signal (Q2) using the phase difference between the first (REFCLK input to 54 via 52) and second clocks (FBCLK input 54) on the basis of a second phase difference set by a delay circuit (52; 52 sets the phase difference between REFCLK and FBCLK, at least in part, according to the delay of 52).
Masuda et al. merely discloses a single delay circuit (52) and fails to explicitly disclose that the single delay circuit (52) includes a “plurality of delay cells”.
However, it is old and well-known to construct a clock delay circuit (such as 52) using a plurality of delay cells. This is further evidenced in Fig. 3A of Quan et al. which discloses a specific delay circuit (304a of Fig. 3A) that includes a plurality of delay cells (each 316, 324, 328 and 334). The delay cell of is minimally is an accurate delay that is minimally dependent on PVT variations (see Col. 5 lines 11-16).
It would have been obvious to replace the delay circuits (including 52) of Masuda et al. with the delay cell of Fig. 3A of Quan et al. for the purpose of having accurate delay cells with minimal dependency on PVT variations.
With respect to claim 2, the phase-locked loop of claim 1, wherein the lock detection unit activates the first unlock signal to a high logic state when the phase difference between the first clock and the second clock exceeds the first phase difference and maintains the first unlock signal at a low logic state when the phase difference between the first clock and the second clock does not exceed the first phase difference, and activates the second unlock signal to a high logic state when the phase difference between the first and second clocks exceeds the second phase difference and maintains the second unlock signal at a low logic state when the phase difference does not exceed the second phase difference (41 generates Q1 and Q2 as claimed as long as the phase difference is smaller than the delays of 51 and 52 Q1 and Q2 are generated as a low signal. When the phase difference is larger Q1 or Q2 are generated as a high signal, see Col. 5 lines 56-65).
With respect to claim 8, a phase-locked loop (Fig. 1 further details disclosed in Figs. 2 and 5) comprising:
a phase detection unit (22) configured to detect a phase difference between a first clock (REFCLK) and a second clock (VCOCLK. The phase difference of VCOCLK is determined according to the output of 26 which is dependent upon VCOCLK. Thus, the phase difference between REFCLK and VCOCLK is proportional to the phase/frequency shift provided by 26);
a voltage generation unit (23 with 24) configured to generate a control voltage in response to an output signal of the phase detection unit (VCTL);
an oscillating unit (25) configured to generate the second clock that toggles at a frequency corresponding to a level of the control voltage (VCOCLK);
a clock division unit (26 details disclosed in Fig. 5) configured to generate a plurality of divided clocks by dividing the second clock at a plurality of ratios (1/n and 1/(n+1) clock based on the above ratios); and
a lock detection unit (41 of Fig. 2) configured to generate a first unlock signal (Q1) using the phase difference between the first and second clocks (difference based on REFCLK input to 53 and FBCLK input to 53 via 51) on the basis of a first phase difference corresponding to a cycle of a selected divided clock (the difference is on a basis of the cycle of the selected divide clock, since FBCLK input to 53 is based on the divided clock FBCLK which is the selected divided clock) and to generate a second unlock signal (Q2) using the phase difference between the first (REFCLK input to 54 via 52) and second clocks (FBCLK input 54) on the basis of a second phase difference set by a delay circuit (52; 52 sets the phase difference between REFCLK and FBCLK, at least in part, according to the delay of 52), and to generate a lock completion signal in response to the first and second unlock signals (55 generating LOCK).
Masuda et al. merely discloses a single delay circuit (52) and fails to explicitly disclose that the single delay circuit (52) includes a “plurality of delay cells”.
However, it is old and well-known to construct a clock delay circuit (such as 52) using a plurality of delay cells. This is further evidenced in Fig. 3A of Quan et al. which discloses a specific delay circuit (304a of Fig. 3A) that includes a plurality of delay cells (each 316, 324, 328 and 334). The delay cell of is minimally is an accurate delay that is minimally dependent on PVT variations (see Col. 5 lines 11-16).
It would have been obvious to replace the delay circuits (including 52) of Masuda et al. with the delay cell of Fig. 3A of Quan et al. for the purpose of having accurate delay cells with minimal dependency on PVT variations.
With respect to claim 9, the phase-locked loop of claim 8, wherein the lock detection unit activates the first unlock signal by detecting when the phase difference between the first clock and the second clock exceeds the first phase difference, activates the second unlock signal by detecting when the phase difference exceeds the second phase difference, and the generated lock completion signal indicates that the lock has been completed when both the first and second unlock signals are deactivated (41 generates Q1 and Q2 as claimed as long as the phase difference is smaller than the delays of 51 and 52 Q1 and Q2 are generated as a low signal. When the phase difference is larger Q1 or Q2 are generated as a high signal, see Col. 5 lines 56-65).
Claim 14 is rejected for essentially the same reasons as claims 1 and 2.
Allowable Subject Matter
Claims 3-7, 10-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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