DETAILED ACTION
This Office action is in response to the communication filed on May 22, 2025. Claims 1-20 are currently pending in this application. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application filed September 19, 2020 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged and considered. However, the prior-filed application did not have written description of the second capacitor electrode first protrusion portion and the second capacitor electrode second protrusion portion, and other limitations also omitted in the drawings as mentioned below. They have the effective filing date of the filing date of the application on May 22, 2025.
Drawings
The drawings are objected to because the drawings are not of a sufficient quality and appear faded or blurry to read and it is difficult to map the reference numbers to the corresponding parts in the drawings.
The subject matter of this application omits illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c), specifically pertaining to: “the second capacitor electrode of the first sub-pixel comprises a first protrusion portion and a second protrusion portion which are both protruded along a first direction,”
“the second electrode portion of the second capacitor electrode comprises an electrode protrusion portion, and the electrode protrusion portion is extended along the first direction,” and
“first electrode portions of second capacitor electrodes of the first sub-pixel and the second sub-pixel are in an integrated structure,”
“the first electrode portion and the second electrode portion of the second capacitor electrode are on opposite sides of the connection electrode,” and “the third capacitor electrode comprises a first electrode protrusion portion protruding along the first direction and a second electrode protrusion protruding along a second direction, and the second direction intersects with the first direction” as well as similar limitations not illustrated. Protrusions are shown with respect to data or first scan line connecting portion 311 includes a main body portion 321 and an extension portion 322, and the extension portion 322 is a portion of the main body portion 321 in Fig. 10B, but with respect to the second capacitor electrode. Previously, by providing the connection electrode 342, it helps to further reduce the resistance on the power line 270b, where the connection electrode has a protrusion as in the priority document, but this is not with respect to the second capacitor electrode of the storage capacitor.
No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2006/0232505 A1 by Asada in view of U.S. Patent Publication 2017/0004769 A1 by Arokia et al. (“Arokia,”) and further in view of U.S. Patent Publication 2024/0257749 A1 by Son et al. (“Son.”)
Regarding claim 1, Asada teaches a display wherein the first sub-pixel comprises a pixel circuit (Fig. 2 was a pixel driving circuit of a display), and the pixel circuit comprises
a data writing sub-circuit (Fig. 3, transistor 103), a storage sub-circuit (Fig. 3, storage capacitor CH), a driving sub-circuit (Fig. 3, transistor 302),
the data writing sub-circuit is electrically connected with a first terminal of the storage sub-circuit (Fig. 3, terminal of transistor Qn connected to a first terminal of capacitor CH), and is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal (Fig. 3, data signal Vd transmitted according to scanning signal 101 to the first terminal of the capacitor CH),
the driving sub-circuit comprises a control electrode (Fig. 3, gate electrode of transistor 302), a first electrode (Fig. 3, terminal of transistor 302 connected to scanning line 101) and a second electrode (Fig. 3, terminal of transistor 302 connected to first terminal of resistor RL), the control electrode of the driving sub-circuit is electrically connected with the first terminal of the storage sub-circuit Fig. 3, gate electrode of transistor 302 connected to the first terminal of capacitor CH)
the first electrode of the driving sub-circuit is configured to receive a first power supply voltage (Fig. 3, terminal of transistor 302 connected to scanning line 101), and the driving sub-circuit is configured to drive the light element in response to a voltage at the first terminal of the storage sub-circuit ([0006], the data signal transferred to the pixel electrode 5903 is held by the storage capacitor 5906 and the capacitance Cpix of the liquid crystal. The liquid crystal switches in accordance with the held pixel voltage Vpix, and as shown by the light transmittance T1); and
the storage sub-circuit comprises a storage capacitor, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, and the first capacitor electrode and the second capacitor electrode respectively serve as the first terminal and a second terminal of the storage sub-circuit (Fig. 3, [0154], capacitor CH has electrode at node Va as second terminal and voltage holding capacitor electrode 105 as first terminal);
However, Asada does not teach display substrate, comprising a base substrate and a sub-pixel on the base substrate, the first electrode of the driving sub-circuit is configured to receive a first power supply voltage, a second terminal of the resistance device is configured to be electrically connected with a first electrode of a light-emitting element, and the driving sub-circuit is configured to drive the light-emitting element to emit light in response to a voltage at the first terminal of the storage sub-circuit.
Asada provides a resistor provides stability when a voltage shift referred to as feed-through voltage occurs through the capacitance between the gate and source of the transistor (Qn) when the data signal transferred to the pixel electrode 5903 is held by the storage capacitor 5906. In the analogous art of active matrix pixel circuits, Arokia similarly teaches a feedback circuit between a storage capacitor and OLED light emitting display element on a display substrate (Arokia Fig. 1; [0012]). The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels (Arokia [0011]). The feedback circuit comprising a resistor connected between the second terminal of said drive use transistor and a supply potential and provided a voltage is used to adjust the programming voltage of the pixel (Arokia [0010]). It would have been obvious before the effective filing date of the invention to have switched the liquid crystal with the light emitting element and driving transistor providing a current. As current through OLED strongly depends on the characteristic parameters of the driving and programming TFT. Since the characteristic parameters of a TFT, particularly, the threshold voltage under bias stress, vary by time, and such changes may differ from pixel to pixel, the induced image distortion may be unacceptably high. The programming voltage can be accurately adjusted by an external control unit through the use of feedback voltage generated by the on-pixel feedback circuit. The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current by the driving transistor despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels. One of the methods that has been employed to make the current driving circuit less sensitive to the shift in the threshold voltage is programming the pixel with current instead of voltage (Arokia Fig. 1; [0010]-[0011] and [0007]).
Asada in view of Arokia does not teach the second capacitor electrode of the first sub-pixel comprises a first protrusion portion and a second protrusion portion which are both protruded along a first direction.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel, the capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction. It would have been obvious before the effective filing date to have had a shared metal layer for a capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 2, Asada in view of Arokia does not teach the display substrate according to claim 1, wherein the second capacitor electrode comprises a first electrode portion and a second electrode portion which are spaced apart in the first direction; and the first protrusion portion and the second protrusion portion are both a part of the second capacitor electrode.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel, the capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction. It would have been obvious before the effective filing date to have had a shared metal layer for a capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 3, Asada in view of Arokia does not teach display substrate according to claim 2, wherein the second electrode portion of the second capacitor electrode comprises an electrode protrusion portion, and the electrode protrusion portion is extended along the first direction.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel, the capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction. It would have been obvious before the effective filing date to have had a shared metal layer for a capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 4, Asada in view of Arokia does not teach display substrate according to claim 2, further comprising a second sub-pixel which is adjacent to the first sub-pixel in the first direction, wherein first electrode portions of second capacitor electrodes of the first sub-pixel and the second sub-pixel are in an integrated structure.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction. It would have been obvious before the effective filing date to have had a shared metal layer for a capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 5, Asada of the combination of references further teaches the display substrate according to claim 2, wherein the pixel circuit further comprises a resistance device (Fig. 3, resistor RL), a first terminal of the resistance device is electrically connected with the second electrode of the driving sub-circuit (Fig. 3, terminal of driving transistor 302 connected to first terminal of resistor RL);, and a second terminal of the resistance device is configured to be electrically connected with the light-emitting element (Fig. 3, terminal of liquid crystal 109 was connected to the second terminal of resistor RL via first terminal of resistor RL); and the resistance device and the control electrode of the driving sub-circuit are in a same layer and insulated from each other, and a resistivity of the resistance device is higher than a resistivity of the control electrode of the driving sub-circuit (Fig. 4; [0005] and [0160]; the transistor (Qn) 103 was a p- type polysilicon thin film transistor and resistor RL is formed from a p-type lightly doped semiconductor thin film 404 formed at the same time as a lightly doped drain 403 of the transistor Qn 103 and the gate/control was insulated above 402. As only the drain was lightly doped, the resistivity of the transistor Qn 103 was more than the lightly doped resistor as lightly doping increases resistivity inherently also defined in Applicant paragraph [0089]).
Regarding claim 6, Asada of the combination of references further teaches the display substrate according to claim 5, wherein the resistance device and the control electrode of the driving sub-circuit are both made of a polysilicon material (Fig. 4; [0005] and [0160]; the transistor (Qn) 103 was a p- type polysilicon thin film transistor and resistor RL is formed from a p-type lightly doped semiconductor thin film 404 formed at the same time as a lightly doped drain 403 of the transistor Qn 103).
Regarding claim 7, Asada of the combination of references further teaches the display substrate according to claim 5, wherein the first sub-pixel further comprises a first connection electrode (Fig. 4, metal layer 404), and the first connection electrode connects the first terminal of the resistance device with the second electrode of the driving sub-circuit (Figs. 1 and 4, the metal layer 404 adjacent to layer 406 connects p+ terminal of driving transistor 403 to resistance layer RL 404 as in [0199]).
Regarding claim 8, Asada of the combination of references further teaches the display substrate according to claim 7, wherein the connection electrode and the second capacitor electrode are in a same layer and insulated from each other (Fig. 16, [0161], This is because if the source/drain p+ layer and the i layer are contacted, an extremely high short key resistance is formed, and a resistance satisfying equation (1) can no longer be formed on the small area. Similarly, a p− layer 404 is formed between the p+ electrode 403 connected to the voltage holding capacitor electrode 105, and the i layer 501). Asada in view of Arokia does not teach the first electrode portion and the second electrode portion of the second capacitor electrode are on opposite sides of the connection electrode.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR where the second capacitor electrode and metal electrode of Asada in view of Arokia was disposed. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction on opposite sides. It would have been obvious before the effective filing date to have had a shared metal layer for a capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 13, Asada of the combination of references further teaches the display substrate according to claim 1, the first capacitor electrode serves as the control electrode of the driving sub-circuit (Fig. 3, [0154], capacitor CH has electrode at node Va connected to gate of driving transistor 302 as second terminal and voltage holding capacitor electrode 105 as first terminal connected to gate via node Va);
Asada in view of Arokia does not teach wherein the first capacitor electrode comprises a first protrusion portion and a second protrusion portion which are both protruded in a second direction, and the second direction intersects with the first direction.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR where the second capacitor electrode and metal electrode of Asada in view of Arokia was disposed. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction on opposite sides. Patterns Ma1, Ma2, and Ma3 of a second metal layer are formed as independent patterns or island patterns that are separated between neighboring red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B. The patterns of the second metal layer are divided into a second-first capacitor electrode (or top electrode) Ma1 disposed in the red sub-pixel R, a second-second capacitor electrode Ma2 disposed in the green sub-pixel G, and a second-third capacitor electrode Ma3 disposed in the blue sub-pixel B (Son [0162]).
It would have been obvious before the effective filing date to have had a shared metal layer for another capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 14, Asada of the combination of references further teaches the display substrate according to claim 1, further comprising a power line extended along the first direction, wherein the power line is configured to provide the first power supply voltage to the first sub-pixel; and in a direction perpendicular to the base substrate, the power line is overlapped with the 3 second protrusion portion of the second capacitor electrode (Fig. 3, terminal of transistor 302 connected to scanning line 101 where one of plural power supply electrodes connected to the scanning line as in Abstract),
Asada in view of Arokia does not teach in a direction perpendicular to the base substrate, the power line is overlapped with the second protrusion portion of the second capacitor electrode.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR where the second capacitor electrode and metal electrode of Asada in view of Arokia was disposed. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction on opposite sides. Patterns Ma1, Ma2, and Ma3 of a second metal layer are formed as independent patterns or island patterns that are separated between neighboring red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B. The patterns of the second metal layer are divided into a second-first capacitor electrode (or top electrode) Ma1 disposed in the red sub-pixel R, a second-second capacitor electrode Ma2 disposed in the green sub-pixel G, and a second-third capacitor electrode Ma3 disposed in the blue sub-pixel B (Son [0162]).
It would have been obvious before the effective filing date to have had a shared metal layer for another capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 17, Asada of the combination of references further teaches the display substrate according to claim 1, further comprising a power line extended along the first electrode, wherein the power line is configured to provide a second power supply voltage to the first sub-pixel, and the second power supply voltage is different from the first power supply voltage (Fig. 3, terminal of transistor 302 connected to scanning line 101 where one of plural power supply electrodes connected to the scanning line as in Abstract).
Asada in view of Arokia did not teach in a direction perpendicular to the base substrate, the power line is overlapped with the first protrusion portion of the second capacitor electrode.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR where the second capacitor electrode and metal electrode of Asada in view of Arokia was disposed. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage such as power lines to which constant voltages are applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103] and [0168]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction on opposite sides. Patterns Ma1, Ma2, and Ma3 of a second metal layer are formed as independent patterns or island patterns that are separated between neighboring red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B.
It would have been obvious before the effective filing date to have had a shared metal layer for another capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 16, Asada of the combination of references further teaches the display substrate according to claim 1, wherein the data writing sub-circuit comprises a first data writing transistor(Fig. 15, Qp), the driving sub-circuit comprises a driving transistor (Fig. 15, Qn), the first data writing transistor is a P-type metal-oxide semiconductor field effect transistor ([0201], the p-type MOS transistor (Qp) 1501 comes on), and the driving transistor is an N-type metal-oxide semiconductor field effect transistor ([0201], data signal Vd input to the signal line is transferred to the gate electrode of the n-type MOS transistor (Qn) 1502); and in a direction parallel to a plate surface of the base substrate, the first data writing transistor and the driving transistor are on opposite sides of the storage capacitor (Fig. 18, Qn 1501, storage capacitor 105, Qp 1502, where an n-type MOS transistor (Qn) 1502 with a gate electrode connected to the other of the source electrode and the drain electrode of the p-type MOS transistor (Qp) as in [0194]).
Regarding claim 17, Asada of the combination of references further teaches the display substrate according to claim 1, wherein the first sub-pixel further comprises a connection electrode; the connection electrode and the second capacitor electrode are in a same layer and insulated from each other (Fig. 16, [0161], This is because if the source/drain p+ layer and the i layer are contacted, an extremely high short key resistance is formed, and a resistance satisfying equation (1) can no longer be formed on the small area. Similarly, a p− layer 404 is formed between the p+ electrode 403 connected to the voltage holding capacitor electrode 105, and the i layer 501), and the connection electrode electrically connects the first capacitor electrode with the data writing sub-circuit (Fig. 4, semiconductor thin film (I layer) 301/501 connected to capacitor 105, p- connection 404, and source-drain electrode (p+) 403 are arranged on layer 400 in a second direction as in [0161] and [0432]).
Regarding claim 18, Asada of the combination of references further teaches the display substrate according to claim 17, wherein the connection electrode comprises a first portion extended along the first direction and a second portion extended along a second direction, the first portion and the second portion are in an integral structure, and the first direction and the second direction are orthogonal to each other; the first portion is electrically connected with the data writing sub-circuit and the second potion is electrically connected with the first capacitor electrode.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR where the second capacitor electrode and metal electrode of Asada in view of Arokia was disposed. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction on opposite sides. Patterns Ma1, Ma2, and Ma3 of a second metal layer are formed as independent patterns or island patterns that are separated between neighboring red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B. The patterns of the second metal layer are divided into a second-first capacitor electrode (or top electrode) Ma1 disposed in the red sub-pixel R, a second-second capacitor electrode Ma2 disposed in the green sub-pixel G, and a second-third capacitor electrode Ma3 disposed in the blue sub-pixel B (Son [0162]). Therefore, as second metal layer of the first electrode was also an integral structure amongst sub-pixels including within the semiconductor layer 400 including connection electrode 404 in Asada.
It would have been obvious before the effective filing date to have had a shared metal layer for another capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 19, Asada of the combination of references further teaches the display substrate according to claim 17, wherein along a second direction, the data writing sub-circuit, the connection electrode and the driving sub-circuit are sequentially arranged, and the first direction and the second direction are orthogonal to each other (Fig. 4, semiconductor thin film (I layer) 301/501 connected to scanning line 101 , p- connection 404, and source-drain electrode (p+) 403 are arranged on layer 400 in a second direction as in [0161] and [0432]).
Regarding claim 20, Asada of the combination of references further teaches a display device, comprising the display substrate of claim 1 and the light-emitting element (Fig. 1, FIG. 1 is a diagram showing a first embodiment of a liquid crystal display device of the present invention).
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2006/0232505 A1 by Asada in view of U.S. Patent Publication 2017/0004769 A1 by Arokia and U.S. Patent Publication 2024/0257749 A1 by Son, and further in view of U.S. Patent Publication 2021/0183968 A1 by Kim et al. (“Kim.”)
Regarding claim 9, Asada in view of Arokia and Son does not teach the display substrate according to claim 1, wherein the storage capacitor further comprises a third capacitor electrode; and in a direction perpendicular to the base substrate, the third capacitor electrode is on a side of the first capacitor electrode away from the second capacitor electrode, and is configured to be electrically connected with the second capacitor electrode.
In the analogous art of display pixel circuits, Kim teaches a first capacitor electrode also connected as the third capacitor electrode that was connected to third capacitor electrode also connected as the first capacitor electrode formed away on the third capacitor on the other side of the second capacitor electrode. The first capacitor electrode (C11) and the third capacitor electrode (C13) may be connected with each other on a side of the first capacitor away from the second capacitor electrode, the same voltage may be applied to the third capacitor electrode (C13) and the first capacitor electrode (C11). Accordingly, a first capacitance (C1a) is formed between the first capacitor electrode (C11) and the second capacitor electrode (C12), a second capacitance (C1b) is formed between the second capacitor electrode (C12) and the third capacitor electrode (C13) electrically, and the sum of the first capacitance (C1a) and the second capacitance (C1b) may be a total capacitance of the first capacitor (C1). As a result, as the total capacitance of the first capacitor (C1) is increased (Kim Figs. 3 and 5; [0119]). As shown in Figs 5 and 3, the third capacitor electrode (C13) was in a direction perpendicular to the base substrate 210 and the third capacitor electrode was a rectangle that was symmetrical in a parallel horizontal direction and it was also symmetrical in a parallel vertical direction (Kim Figs. 3 and 5; [0119]). It would have been obvious to have added a third capacitor electrode to the storage capacitor of Asada as modified by Arokia and Son. One having ordinary skill in the art would have been motivated to as a result, as the total capacitance of the first capacitor (C1) is increased, it is possible to stably drive the display apparatus 100 (Kim Figs. 3 and 5; [0119]).
Regarding claim 10, Asada in view of Arokia does not teach the display substrate according to claim 9, wherein the third capacitor electrode comprises a first electrode protrusion portion protruding along the first direction and a second electrode protrusion protruding along a second direction, and the second direction intersects with the first direction.
However, in the analogous art of capacitor electrodes in display panels, Son teaches display panel included a second-first capacitor Ca1, a second-second capacitor Ca2, and a second-third capacitor Ca2 disposed in a circuit layer CIR where the second capacitor electrode and metal electrode of Asada in view of Arokia was disposed. The pattern Mb of the first metal layer is a common electrode (or lower electrode) of the second-first capacitor Ca1, second-second capacitor Ca2, and second-third capacitor Ca3, which is continuously connected to the red sub-pixel R, green sub-pixel G, and blue sub-pixel B and is shared among the red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A constant voltage Vdc or a pixel driving voltage EVDD is applied to the pattern Mb of the first metal layer. (Son Figs. 9-10; [0101]-[0103]). For a first red sub-pixel and second green sub-pixel, the integrated capacitor common electrode had a main body and two extensions protruding out of the main body in a first direction on opposite sides. It would have been obvious before the effective filing date to have had a shared metal layer for another capacitor electrode between sub-pixels when connected to a constant voltage line like in Asada in view of Arokia. One having ordinary skill in the art would have been motivated to have driven the pixels at high luminance without increasing the data voltage and without expanding the data voltage range by optimizing the capacitance of the second capacitor, which is intended to reduce the loss of the data voltage, for each of the sub-pixels of the first color, the second color and the third color in the pixel when connected to a constant voltage (Son Figs. 9-10; [0022]).
Regarding claim 11, Asada in view of Arokia and Son does not teach the display substrate according to claim 9, wherein the third capacitor electrode of the storage capacitor is a first region of the base substrate, and the second capacitor electrode is overlapped with the first capacitor electrode in the direction perpendicular to the base substrate.
In the analogous art of display pixel circuits, Kim teaches a first capacitor electrode also connected as the third capacitor electrode that was connected to third capacitor electrode also connected as the first capacitor electrode formed away on the third capacitor on the other side of the second capacitor electrode. The first capacitor electrode (C11) and the third capacitor electrode (C13) may be connected with each other on a side of the first capacitor away from the second capacitor electrode, the same voltage may be applied to the third capacitor electrode (C13) and the first capacitor electrode (C11). Accordingly, a first capacitance (C1a) is formed between the first capacitor electrode (C11) and the second capacitor electrode (C12), a second capacitance (C1b) is formed between the second capacitor electrode (C12) and the third capacitor electrode (C13) electrically, and the sum of the first capacitance (C1a) and the second capacitance (C1b) may be a total capacitance of the first capacitor (C1). As a result, as the total capacitance of the first capacitor (C1) is increased (Kim Figs. 3 and 5; [0119]). As shown in Figs 5 and 3, the third capacitor electrode (C13) was in a direction perpendicular to the base substrate 210 and the third capacitor electrode was a rectangle that was symmetrical in a parallel horizontal direction and it was also symmetrical in a parallel vertical direction (Kim Figs. 3 and 5; [0119]). It would have been obvious to have added a third capacitor electrode to the storage capacitor of Asada as modified by Arokia and Son. One having ordinary skill in the art would have been motivated to as a result, as the total capacitance of the first capacitor (C1) is increased, it is possible to stably drive the display apparatus 100 (Kim Figs. 3 and 5; [0119]).
Regarding claim 12, Asada of the combination of references further teaches the according to claim 9, a doping concentration of the contact region is higher than a doping concentration the electrode region Fig. 4; [0005] and [0160]; the transistor (Qn) 103 was a p- type polysilicon thin film transistor and resistor RL is formed from a p-type lightly doped semiconductor thin film 404 formed at the same time as a lightly doped drain 403 of the transistor Qn 103 and the gate/control was insulated above 402. As only the drain was lightly doped, the resistivity of the transistor Qn 103 was more than the lightly doped resistor as lightly doping increases resistivity inherently also defined in Applicant paragraph [0089] and therefore, connection by contact region was higher as it was in the lightly doped region 404).
Asada in view Arokia and Son does not teach wherein the third capacitor electrode comprises an electrode region and a contact region, the electrode region is overlapped with the second capacitor electrode in the direction perpendicular to the base substrate, and the second capacitor electrode is configured to be electrically connected with the electrode region through the contact region.
In the analogous art of display pixel circuits, Kim teaches a first capacitor electrode also connected as the third capacitor electrode that was connected to third capacitor electrode also connected as the first capacitor electrode formed away on the third capacitor on the other side of the second capacitor electrode. The first capacitor electrode (C11) and the third capacitor electrode (C13) may be connected with each other on a side of the first capacitor away from the second capacitor electrode, the same voltage may be applied to the third capacitor electrode (C13) and the first capacitor electrode (C11). Accordingly, a first capacitance (C1a) is formed between the first capacitor electrode (C11) and the second capacitor electrode (C12), a second capacitance (C1b) is formed between the second capacitor electrode (C12) and the third capacitor electrode (C13) electrically, and the sum of the first capacitance (C1a) and the second capacitance (C1b) may be a total capacitance of the first capacitor (C1). As a result, as the total capacitance of the first capacitor (C1) is increased (Kim Figs. 3 and 5; [0119]). As shown in Figs 5 and 3, the third capacitor electrode (C13) was in a direction perpendicular to the base substrate 210 and the third capacitor electrode was a rectangle that was symmetrical in a parallel horizontal direction and it was also symmetrical in a parallel vertical direction (Kim Figs. 3 and 5; [0119]). It would have been obvious to have added a third capacitor electrode to the storage capacitor of Asada as modified by Arokia and Son. One having ordinary skill in the art would have been motivated to as a result, as the total capacitance of the first capacitor (C1) is increased, it is possible to stably drive the display apparatus 100 (Kim Figs. 3 and 5; [0119]).
Conclusion
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/MAHEEN I JAVED/Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
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