Prosecution Insights
Last updated: October 02, 2026
Application No. 19/216,234

Scalable, Hierarchical Power Delivery System

Non-Final OA §112§DP
Filed
May 22, 2025
Priority
Aug 25, 2021 — continuation of 11/698,669 +1 more
Examiner
BAE, JI H
Art Unit
Tech Center
Assignee
Apple Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
650 granted / 790 resolved
+22.3% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
20 currently pending
Career history
806
Total Applications
across all art units

Statute-Specific Performance

§101
7.3%
-32.7% vs TC avg
§103
28.6%
-11.4% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
36.1%
-3.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 790 resolved cases

Office Action

§112 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed on 22 May 2026 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. Copies of the following references were not provided: WO 2023028127 KR 20240033275 KR 20250004391 Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The preamble of claim 1 recites a “scalable computing architecture”. The subsequent claim language makes it unclear whether this language further limits the invention or is merely a statement of intended use (and therefore possible non-limiting). The body of the claim does not reference the scalable computing architecture, nor does this language appear to have any meaningful impact on the function of the claimed invention. Claim 1 is therefore rejected as being indefinite. Similar reasoning may be applied to claims 31 and 38. Claim 24 recites the limitation “a particular one of the plurality of power configurations”. Claim 21 has already provided an original recitation for “a particular one...” in line 11. It is unclear whether the language of claim 24 establishes a new “particular one” or is a reference to similar language in claim 21. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 21-37 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11,698,669. Claims 21-23, 26-28, 30, and 35-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 6, 8-13, and 15-20 of U.S. Patent No. 12,346,179. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by, or obvious variants of, the patent claims. Application claims 21-37 recite the same features as recited in claims 1-17, respectively, of the ‘669 patent with some variations in language. For example, application claim 1 recites a “scalable computing architecture” whereas the ‘669 patent claim 1 does not recite this feature. However, ‘669 patent claim 12 recites a scalable computing architecture as a dependent claim. This represents an obvious variant because application claim 1 is anticipated by patent claims 1 and 12 when considered collectively. Similar reasoning may be applied to application claims 21-23, 26-28, 30, and 35-40 and claims 1, 2, 4, 6, 8-13, and 15-20 of the ‘179 patent. The application claims may be compared to the patent claims in the following manner. Application Claims Patent Claims 21 1, 12 22 1, 12 23 1, 12 26 1, 2, 4, 13 27 9, 16 28 6, 15, 30 10, 11, 17, 18 35 4, 13 36 6, 15 37 8, 9, 16 38 19 39 20 40 9, 16 Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references were cited by the Examiner during prosecution of parent Application Nos. 18/326,430 and 17/412,230: Lee et al., U.S. Patent Application Publication No. 20200363850, discloses a system with a plurality of loads, and switching circuitry to selectively connect at least one regulator among a plurality of regulators to power a desired load [abstract; Fig. 1A]. Huang et al., U.S. Patent Application Publication No. 2019/0296644, discloses a hierarchical power delivery system [Fig. 1] comprising a first level [VREG 104] and a second level [IVRs 106-112]. Mercer et al., U.S. Patent Application Publication No. 2013/0335058, discloses a hierarchical power delivery system [Fig. 1] comprising a first level [power bus voltage regulator 101] and a second level [POL voltage regulators 102-104]. Henspeter et al., U.S. Patent Application Publication No. 2022/0187888, discloses a VRM card that is capable of assigning power stages to feedback loop configurations based on a system power property [Fig. 2]. Wu et al., U.S. Patent Application Publication No. 2022/0123656, discloses a two-stage power converter system for a processor [Fig. 2 and 7]. Vinciarelli, U.S. Patent No. 11,228,246, discloses a plurality of power processors comprising first and second power converters coupled in series [Fig. 2]. Kim et al., U.S. Patent Application Publication No. 2021/0382511, discloses a system with a plurality of voltage regulators that are individually enabled when a demand signal exceeds a threshold [para. 0025; Fig. 7]. Muratsu, U.S. Patent Application Publication No. 2020/0036210, discloses a system for charging a battery comprising a plurality of power conversion units, each unit comprising two stages of power converters, the system capable of changing the number of active converters based on current values detected by current detectors [para. 0054; Fig. 1]. Hendin et al., U.S. Patent Application Publication No. 2009/0153108, discloses a power management unit comprising a first and second stage regulator coupled in series with a feedback voltage, and providing an output voltage to a plurality of computer components [Fig. 1 and 2]. Ravichandran, U.S. Patent Application Publication No. 2008/0111534, discloses a circuit with a plurality of subsystems that is provided with power by a plurality of voltage regulators and pass transistors capable of supplying varying amounts of power to the circuit [Fig. 1 and 2]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office Phone: 571-272-7181 Fax: 571-273-7181 ji.bae@uspto.gov
Read full office action

Prosecution Timeline

May 22, 2025
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §112, §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12748476
Power Management in Multi-Die SoCs through Hardware Power Control
2y 6m to grant Granted Sep 29, 2026
Patent 12748454
RELIABLE AND FAULT-TOLERANT CLOCK GENERATION AND DISTRIBUTION FOR CHIPLET-BASED WAFERSCALE PROCESSORS
2y 6m to grant Granted Sep 29, 2026
Patent 12717391
REGULATOR CIRCUIT, AN ELECTRONIC DEVICE INCLUDING THE REGULATOR CIRCUIT, AND A PROCESSOR INCLUDING THE REGULATOR CIRCUIT
2y 8m to grant Granted Aug 25, 2026
Patent 12710797
SYSTEM ON CHIP AND METHOD FOR OPERATING THE SAME
2y 1m to grant Granted Aug 18, 2026
Patent 12710804
Dynamic Management of Data Centers
1y 10m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+20.9%)
2y 8m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 790 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month