Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS submission on 08/14/2025 has been reviewed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 9, 11, 12, and 24 are rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claims 8, 9, 12, and 24, the claims rely on comparative language, stating that the system or method achieves “reduced latency” (Claims 8, 24), “reduced power” (Claims 9, 24), or “reduced error rates” (Claim 12) “when compared to a baseline.” The term “baseline” is a relative term, and the claims themselves fail to provide a specific standard, metric, or reference point for what constitutes this baseline. Because a person having ordinary skill in the art would not be able to determine the objective boundaries of the “baseline” by reading the claims, the scope of the claims cannot be ascertained.
(Examiner’s Note: The Examiner recognizes that the specification provides context for these baselines in paragraphs [0047], [0082], and [0096]—e.g., “a baseline in which equalization is not used.” The Applicant may overcome this rejection by amending the claims to explicitly incorporate these definitions).
Regarding Claim 11, the claim recites a “quasi-static routing path.” The term “quasi-static” is a term of degree. While paragraph [0090] of the specification states that quasi-static paths are updated “not as frequently as those in dynamic routing,” this relies on a subjective standard. It is unclear what objective frequency standard is used to distinguish a “quasi-static” path from a “dynamic” path. Without a defined, objective standard to determine the boundaries of “quasi-static,” the claim is indefinite.
Claim Rejections - 35 USC § 103
Claim(s) 1-8, 1-23, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (U.S. patent 7554355), hereinafter referred to as Chang, in view of Vegas Olmos et al. (U.S. patent 11658796), hereinafter referred to as Vegas Olmos and further in view of Narippatta et al. (U.S. patent application publication 20170300443 A1) referred hereon Narippatta.
Regarding Claim 1, Chang teaches a system comprising a system-on-chip (SoC) comprising one or more processors (DSPs) that operate one or more crossbar switches, and a central crossbar switch facilitating communication between the one or more processors (Chang, Paragraphs [0005], [0011], teaching a multi-processor SoC platform utilizing a crossbar switch matrix to facilitate communication). Chang does not explicitly detail the processors being associated with physical media dependent (PMD) devices. Vegas Olmos teaches optical transceivers comprising one or more physical media dependent (PMD) devices (e.g., lasers/photodiodes) associated with one or more digital signal processors (DSPs) (Vegas Olmos, Paragraphs [0004], [0006]). Before the effective filling date of the claimed inventions, it would have been obvious to integrate the PMDs and DSPs of Vegas Olmos into the SoC crossbar architecture of Chang to efficiently process optical-to-electrical signal conversions directly on-chip. Furthermore, Chang teaches controlling the crossbar switches but lacks explicit details on a lookup table. Narippatta teaches a control unit operable to manage a configuration of the one or more crossbar switches based on a lookup table, wherein the lookup table facilitates data routing between an input and an output (Narippatta, Abstract; Paragraphs [0016], [0078], teaching a lookup table that specifies memory addresses and the configuration of the cross-bar switch to route data). Before the effective filling date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to implement the lookup table (LUT) based crossbar configuration of Narippatta into the SoC crossbar system of Chang and Vegas Olmos. The motivation to do so would be to reduce hardware complexity and allow for dynamic, software-defined reconfiguration of the crossbar routing paths, as explicitly taught by Narippatta (Narippatta, Paragraph [0059]).
Regarding Claim 2, the combination renders obvious the system of claim 1. Claim 2 further recites “wherein the central crossbar switch is operable to facilitate a non-blocking path between the input and the output.” Chang teaches this limitation by disclosing a crossbar switch architecture that allows parallel data communication without data transfer delay, effectively creating non-blocking paths between inputs and outputs (Chang, Paragraph [0011]).
Regarding Claim 3, the combination renders obvious the system of claim 1. Claim 3 further recites “wherein the central crossbar switch is housed within the SoC to facilitate direct communication between the one or more DSPs without using additional routing.” Chang teaches housing the crossbar switch within the multi-processor SoC platform to facilitate direct on-chip communication (Chang, Paragraph [0005]).
Regarding Claim 4, the combination renders obvious the system of claim 1. Claim 4 further recites “further comprising one or more additional crossbars operable to facilitate radix expansion by connecting the one or more crossbar switches to the central crossbar.” Chang teaches expanding the crossbar switch matrix by adding multiplexers (additional crossbars) to the rows or columns to accommodate an increased number of connections (Chang, Paragraphs [0022], [0033]).
Regarding Claim 5, the combination renders obvious the system of claim 1. Claim 5 further recites “further comprising: one or more of an input stage or an output stage including the one or more PMD devices connected directly to the one or more DSPs without external interfacing.” Vegas Olmos teaches transceivers acting as input/output stages where PMD devices are connected directly to DSPs (CDR circuits) within the same module (Vegas Olmos, Paragraphs [0004], [0006]).
Regarding Claim 6, the combination renders obvious the system of claim 1. Claim 6 further recites “wherein: the lookup table includes one or more of optimized routing paths or signal quality metrics; or the lookup table is operable to optimize for one or more of performance or energy efficiency.” Narippatta teaches LUTs containing optimized routing paths (Narippatta, Paragraph [0078]). Vegas Olmos teaches LUTs containing signal quality metrics (equalization data) used to optimize performance and energy efficiency (Vegas Olmos, Paragraphs [0012], [0017]).
Regarding Claim 7, the combination renders obvious the system of claim 1. Claim 7 further recites “wherein the one or more crossbar switches comprises one or more of an 8x8 crossbar switch or a 64 x 64 crossbar switch.” Chang teaches scalable M x N crossbar switches (Chang, Paragraph [0011]). Selecting an 8x8 or 64x64 matrix size is a mere obvious scaling of the M x N architecture based on specific port-density requirements.
Regarding Claim 8, the combination renders obvious the system of claim 1. Claim 8 further recites “wherein the one or more PMDs and the one or more DSPs are embedded within a single chip to facilitate increased signal integrity and reduced latency when compared to a baseline.” Chang teaches embedding architecture on a single SoC (Chang, Paragraph [0005]). Vegas Olmos teaches integrating these components to reduce latency and improve signal integrity (Vegas Olmos, Paragraph [0037]).
Regarding Claim 10, the combination renders obvious the system of claim 1. Claim 10 further recites “further comprising one or more of a switch element, a power management integrated circuit, a crystal oscillator, a microcontroller unit, a printed circuit board, or a cooling fan.” Chang teaches switch elements and microcontroller units (Chang, Paragraphs [0007], [0012]). Incorporating standard supporting hardware such as PCBs, oscillators, PMICs, and cooling fans is notoriously well-known in the art to support SoC operations.
Regarding Claim 11, the combination renders obvious the system of claim 1. Claim 11 further recites “further comprising one or more of a static routing path or a quasi-static routing path.” Chang teaches establishing dedicated, static transfer paths across the crossbar (Chang, Paragraph [0021]).
Regarding Claim 12, the combination renders obvious the system of claim 1. Claim 12 further recites “wherein one or more of the input or the output uses equalization to facilitate increased data integrity and reduced error rates when compared to a baseline.” Vegas Olmos teaches using equalization at inputs and outputs to compensate for signal distortions and increase data integrity (Vegas Olmos, Paragraphs [0014], [0015]).
Regarding Claim 13, the combination renders obvious the system of claim 1. Claim 13 further recites “wherein the lookup table is accessible by a plurality of DSPs across different stages to coordinate configuration of the one or more crossbar switches.” Narippatta teaches LUTs controlling crossbar configurations. Vegas Olmos teaches DSPs across different transceiver stages utilizing lookup tables to coordinate end-to-end link integrity (Vegas Olmos, Paragraphs [0004], [0040]).
Regarding Claim 14, the combination renders obvious the system of claim 1. Claim 14 further recites “wherein a network protocol is operable to control, via an external command received through an Ethernet connection, one or more of: an operation of the one or more crossbar switches, or an updating of the lookup table.” Vegas Olmos teaches utilizing Ethernet network protocols (Vegas Olmos, Paragraph [0018]). Narippatta teaches updating the LUT via software/external commands to dynamically reconfigure the switch (Narippatta, Paragraph [0059]).
Regarding Claim 15, Chang teaches a method comprising receiving, at a first stage, a data signal, and transmitting, from the first stage to a second stage, the data signal, wherein the first stage is operatively connected to the second stage via a first set of one or more crossbar switches (Chang, Paragraphs [0021]-[0022], teaching data transmission across successive stages of multiplexer/crossbar matrices). Chang does not explicitly detail the stages comprising PMD devices and DSPs. Vegas Olmos teaches physical media dependent (PMD) devices associated with digital signal processors (DSPs) at transceiver stages to process data signals (Vegas Olmos, Paragraphs [0004], [0006]). Before the effective filling date of the claimed inventions, it would have been obvious to integrate the PMDs and DSPs of Vegas Olmos into the crossbar stages of Chang to efficiently process optical-to-electrical signals. Furthermore, Chang lacks explicit details on using a lookup table to determine the path. Narippatta teaches determining a first connection path between stages using a lookup table (Narippatta, Abstract; Paragraphs [0016], [0078], teaching a lookup table that specifies memory addresses and the configuration of the cross-bar switch to route data). Before the effective filling date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to determine the connection path using the lookup table of Narippatta within the multi-stage crossbar system of Chang and Vegas Olmos to allow for dynamic, software-defined reconfiguration of routing paths (Narippatta, Paragraph [0059]).
Regarding Claim 16, the combination renders obvious the method of claim 15. Claim 16 further recites “further comprising: transmitting, from the second stage to a third stage, the data signal, wherein the second stage is operatively connected to the third stage via a second set of one or more crossbar switches; and determining, at the one or more DSPs, a second connection path between the second stage and the third stage using the lookup table.” Chang teaches multi-stage crossbar switch architectures where data is transmitted across successive stages (e.g., first, second, and third stages) (Chang, Paragraphs [0021]-[0022]). Narippatta teaches utilizing LUTs to determine routing paths. It would have been obvious to apply the LUT-based path determination of Narippatta to a third stage in the multi-stage switch fabric of Chang to ensure end-to-end routing across the entire network path.
Regarding Claim 17, the combination renders obvious the method of claim 16. Claim 17 further recites “further comprising facilitating a non-blocking path between the first stage and the third stage.” Chang teaches configuring the crossbar matrix to facilitate parallel data communication without data transfer delay, effectively creating non-blocking paths across multiple stages (Chang, Paragraph [0011]).
Regarding Claim 18, the combination renders obvious the method of claim 15. Claim 18 further recites “further comprising connecting the first stage to one or more additional crossbars to facilitate radix expansion.” Chang teaches expanding the crossbar switch matrix by adding multiplexers (additional crossbars) to accommodate an increased number of inputs/outputs (Chang, Paragraphs [0022], [0033]).
Regarding Claim 19, the combination renders obvious the method of claim 15. Claim 19 further recites “wherein the first set of one or more crossbar switches comprises one or more of an 8x8 crossbar switch or a 64 x 64 crossbar switch.” Chang teaches scaling the crossbar switches to an M x N matrix (Chang, Paragraph [0011]). It would have been obvious to scale the crossbar switch to an 8x8 or 64x64 matrix based on specific port-density requirements.
Regarding Claim 20, the combination renders obvious the method of claim 15. Claim 20 further recites “wherein the lookup table includes one or more of a pre-calculated loss profile or a bandwidth roll-off characteristic for the first connection path between the first stage and the second stage.” Vegas Olmos teaches that LUTs contain equalization data (e.g., pre-cursor and post-cursor taps) that match the inverse of the channel transfer function to compensate for signal distortions and physical link characteristics (Vegas Olmos, Paragraphs [0015], [0023]). It would have been obvious to include pre-calculated loss profiles in the LUT to accurately equalize the signal across the connection path.
Regarding Claim 21, the combination renders obvious the method of claim 15. Claim 21 further recites “further comprising dynamically reconfiguring the connection path between the first stage and the second stage based on data stored in the lookup table to optimize data transmission across the first stage and the second stage.” Narippatta explicitly teaches dynamically reconfiguring the crossbar routing paths by reprogramming the lookup table (Narippatta, Paragraph [0059]).
Regarding Claim 22, the combination renders obvious the method of claim 15. Claim 22 further recites “further comprising: updating the lookup table in real-time based on one or more of a change in a network condition or a change in a network configuration.” Vegas Olmos teaches that the lookup table of the CDR circuits can be reconfigured during real-time operation of the computer network system to adapt to changing conditions (Vegas Olmos, Paragraph [0017]). Narippatta similarly teaches updating the LUT via software (Narippatta, Paragraph [0059]).
Regarding Claim 23, the combination renders obvious the method of claim 15. Claim 23 further recites “further comprising calculating, at the one or more DSPs, an optimal data path between the first stage and the second stage based on a comparison of a current network condition to a stored profile in the lookup table.” Vegas Olmos teaches that the DSPs (CDR circuits) repeatedly tune the LUT weights until the communication data satisfies a defined quality criterion based on current channel conditions (Vegas Olmos, Paragraph [0024]). It would have been obvious to use these DSP calculations in conjunction with the LUT routing profiles of Narippatta to determine the optimal data path.
Claim 25 is rejected under 35 U.S.C. § 103 as being unpatentable over Chang, Vegas Olmos, and Narippatta. Regarding Claim 25, the combination renders obvious the method of claim 15. Claim 25 further recites “further comprising adjusting a configuration of the one or more crossbar switches in response to detected packet transmission to maintain a quality of service.” Narippatta teaches adjusting the crossbar configuration to route specific data flows/packets (Narippatta, Paragraphs [0011], [0059]). Vegas Olmos teaches adjusting the system configuration (tuning the LUTs and DSPs) until the communication data satisfies a defined quality criterion/metric (Vegas Olmos, Paragraph [0024]). It would have been obvious to adjust the crossbar switch configuration in response to packet transmissions to maintain the required quality of service (QoS) for the network.
Claim(s) 9, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (U.S. patent 7554355), hereinafter referred to as Chang, in view of Vegas Olmos et al. (U.S. patent 11658796), hereinafter referred to as Vegas Olmos and further in view of Narippatta et al. (U.S. patent application publication 20170300443 A1) referred hereon Narippatta and further in view of Aizawa (U.S. patent 7130177) referred hereon Aizawa.
Claim 9 is rejected under 35 U.S.C. § 103 as being unpatentable over Chang, Vegas Olmos, and Narippatta, and further in view of Aizawa. Regarding Claim 9, the primary combination renders obvious the system of claim 1 but does not explicitly detail passive crossbars using MEMS. Claim 9 further recites “further comprising one or more passive crossbars using microelectromechanical systems (MEMS) to facilitate reduced power when compared to a baseline.” Aizawa teaches the use of passive microelectromechanical systems (MEMS) as switching devices, explicitly noting that MEMS switches are “lower in power consumption” than conventional baseline switches (Aizawa, Paragraph [0007]). Before the effective filling date of the claimed inventions, it would have been obvious to implement the crossbar switches of the primary combination using the MEMS switching devices of Aizawa to achieve the predictable result of reduced power consumption.
Claim 24 is rejected under 35 U.S.C. § 103 as being unpatentable over Chang, Vegas Olmos, and Narippatta, and further in view of Aizawa. Regarding Claim 24, the primary combination renders obvious the method of claim 15. Claim 24 further recites “further comprising using a passive crossbar switch within the first stage or the second stage to one or more of reduce power consumption or reduce latency when compared to a baseline measured using an active switching component, wherein the passive crossbar uses microelectromechanical systems (MEMS) to connect the input and the output.” The primary combination teaches crossbar switching but lacks the explicit disclosure of using passive MEMS. Aizawa teaches using MEMS as switching devices to connect inputs and outputs, explicitly noting that such MEMS switches are “lower in power consumption” than conventional baseline active switches (Aizawa, Paragraph [0007]). Before the effective filling date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to perform the method of Claim 24 by using the MEMS switching devices of Aizawa within the crossbar stages of the primary combination to reduce overall power consumption.
Conclusion
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/TIM T VO/Supervisory Patent Examiner, Art Unit 2138
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